Alpha & Omega Semiconductor Corporation

Aplha and Omega Semiconductor Incorporated

John Chen

Hong Chang

Hamza Yilmaz

Anup Bhalla

Yeeheng Lee

Jongoh Kim

Xiaobin Wang

Wenjun Li

Madhur Bobde

Daniel Ng

Moses Ho

Wilson Ma

Sik Lui

Lingpeng Guan

Daniel S Calafut

Yi Qiang Su

Yongping Ding

Limin Weng

Il Kwan Lee

Sung-Shan Tai

Lingping Guan

Lei Zhang

Gary Chen

Shekar Mallikarjunaswamy

Tiesheng Li

YongZhong Hu

Yangping Ding

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a 'Gap Filler' layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The 'Gap Filler' layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

Nano-tube MOSFET technology and devices

A semiconductor power device formed in a semiconductor substrate that includes a plurality of trenches formed at a top portion of the semiconductor substrate. The trenches extend laterally across the semiconductor substrate along a longitudinal direction and each trench has a nonlinear portion thus the nonlinear portion has a trench sidewall perpendicular to the longitudinal direction of the trench. A plurality of trench bottom dopant regions are formed below the trench bottom surface. A sidewall dopant region is formed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

Process method and structure for high voltage MOSFETs

A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.

MOSFET device and fabrication

This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.

Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Nanotube semiconductor devices

Forming a semiconductor device on a semiconductor substrate having a substrate top surface includes: forming a gate trench extending from the substrate top surface into the semiconductor substrate; forming a gate electrode in the gate trench; forming a curved sidewall portion along at least a portion of a sidewall of the gate trench; forming a body region adjacent to the gate trench; forming a source region embedded in the body region, including disposing source material in a region that is along at least a part of the curved sidewall portion; forming a gate top dielectric layer over the gate electrode and having a top side that is below at least a portion of the source region; and forming a metal layer over at least a portion of a gate trench opening and at least a portion of the source region.

Fabrication of shielded gate trench MOSFET with increased source-metal contact

Semiconductor devices are formed using a pair of thin epitaxial layers (nanotubes) of opposite conductivity type formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes a first termination cell formed in the termination area at an interface to the active area, the termination cell being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the first termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

Termination structure for nanotube semiconductor devices

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a termination structure is formed in the termination area and includes an array of termination cells formed in the termination area, the array of termination cells including a first termination cell at an interface to the active area to a last termination cell, each termination cell in the array of termination cells being formed in a mesa of the first semiconductor layer and having a first width; and an end termination cell being formed next to the last termination cell in the termination area, the end termination cell being formed in an end mesa of the first semiconductor layer and having a second width greater than the first width.

Nanotube termination structure for power semiconductor devices

In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Top drain LDMOS

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region.

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Palo Alto, CA, United States of America

John Chen