Intel Corporation

Tahoe Research, Ltd.

John Charles Weast

Abhishek R Appu

Joydeep Ray

Altug Koker

Linda L Hurd

Dukhwan Kim

Mike B Macpherson

Sara S Baghsorkhi

Xiaoming Chen

Elmoustapha Ould-Ahmed-Vall

Anbang Yao

Ping Tak Tang

Michael S Strickland

Prasoonkumar Surti

Justin E Gottschlich

Chandrasekaran Sakthivel

Liwei Ma

Balaji Vembu

Narayan Srinivasa

Feng Chen

Ben J Ashbaugh

Kamal Sinha

Nadathur Rajagopalan Satish

Farshad Akhbari

Vasanth Ranganathan

Sanjeev S Jahagirdar

Nicolas C Galoppo Von Borries

Kevin Nealis

Barath Lakshmanan

Glen J Anderson

Tobias Max Kohlenberg

Tatiana Shpeisman

Brian David Johnson

Giuseppe Beppe Raffa

Eriko Nurvitadhi

Rajkishore Barik

Lenitra M Durham

Tsung-Han Lin

Timothy J Gresham

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Deepak Shashidhar Vembar

Cory J Booth

Sherine Abdelhak

Kathy Yuen

Neelay Pandit

Corey Kukis

Praneetha Kotha

Rajesh Poornachandran

Tsung-Yuan Charles Tai

Ren Wang

Arvind A Kumar

Kristoffer Fleming

Jennifer Anne Healey

Joshua Boelter

Daniel S Lake

Tao Zhao

Zhonghong Ou

Rita H Wouhaybi

Omesh Tickoo

Mike MacPherson

Dennis M Morgan

Vinayak Honkote

Brett P Wang

Joshua Ekandem

Travis T Schluessler

Manoj R Sastry

Ankur N Shah

Ignacio Javier Alvarez

Marcio Rogerio Juliato

Liuyang L Yang

Shabbir Ahmed

Christopher N Gutierrez

Jonathan Kennedy

Stanley T Mo

John B Vicente

Gunner D Danneels

Robert L Vaughn

Vuk Lesi

Lama Nachman

Adam Jordan

Joshua J Ratcliff

Wendy March

Jeremy Bottleson

Karthik Narayanan

Riccardo Mariani

Peggy J Irelan

Maria Soledad Elli

Jim W Edwards

Ryan Scott Brotman

Olufemi B Oluwafemi

Umberto Santoni

Dibyendu Ghosh

Kenneth T Anderson

Eric Lewallen

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

Technologies for displaying public and private images includes a display device and one or more user viewing devices. The display device is configured to display or generate a personalized image or video that is viewable by an authorized user viewing device and not viewable by unauthorized viewing devices. To facilitate the display of the personalized images, the display device and the user viewing device(s) may negotiate a display protocol to be used by the display device to display the personalized image in a private manner. In some embodiment, the display device may also display a public image or video that is viewable by unauthorized viewing devices and/or individuals without viewing devices.

Technologies for presenting public and private images

Systems and methods may provide for sending a sound wave signal and measuring a body conduction characteristic of the sound wave signal. Additionally, a user authentication may be performed based at least in part on the body conduction characteristic. In one example, the body conduction characteristic includes one or more of a timing, a frequency or an amplitude of the sound wave signal after passing through one or more of bone or tissue.

Authentication through tissue-conducted sound

An automated driving system includes a security companion subsystem to access data generated at a compute subsystem of the automated driving system, which indicates a determination by the compute subsystem associated with an automated driving task. The security companion subsystem determines whether the determination is safe based on the data. The security companion subsystem is configured to realize a higher safety integrity level than the compute subsystem.

Independent safety monitoring of an automated driving system

One embodiment provides a general-purpose graphics processing unit comprising a dynamic precision floating-point unit including a control unit having precision tracking hardware logic to track an available number of bits of precision for computed data relative to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

Compute optimizations for low precision machine learning operations

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Various aspects are related to a map representation system including one or more processors configured to: obtain operation task data, the operation task data indicating one or more operation tasks associated with an operation of one or more autonomous agents within a corresponding operating space; and obtain operation task specific map data as a function of the operation task data, the operation task specific map data representing the operating space corresponding to the one or more operation tasks.

Map representation system and method for operating an autonomous agent

A controller including a processor configured to obtain a message from a task performing agent of a group of task performing agents allocated to a plurality of tasks, wherein the message comprises information about one or more assessments of the task performing agent, wherein the one or more assessments are based on a sensing process performed by one or more sensors of the task performing agent, wherein the task performing agent is an autonomous machine or a human agent equipped with sensors; and allocate a task of the plurality of tasks to the task performing agent, based on the information and based on whether the task performing agent is an autonomous machine or a human agent.

Autonomous machine collaboration

According to various aspects, a controller for an automated machine may include: one or more processors configured to: obtain a message from a further automated machine in accordance with a communication protocol, the message including a first result of a first sensing process that the further automated machine performs; and determine an assessment of the automated machine based on the first result and based on a second result of a second sensing process that the automated machine performs.

Automated machines and systems

One embodiment provides a multi-chip module accelerator usable to execute tensor data processing operations a multi-chip module. The multi-chip module may include a memory stack including multiple memory dies and parallel processor circuitry communicatively coupled to the memory stack. The parallel processor circuitry may include multiprocessor cores to execute matrix multiplication and accumulate operations. The matrix multiplication and accumulate operations may include floating-point operations that are configurable to include two-dimensional matrix multiply and accumulate operations involving inputs that have differing floating-point precisions. The floating-point operations may include a first operation at a first precision and a second operation at a second precision. The first operation may include a multiply having at least one 16-bit floating-point input and the second operation may include an accumulate having a 32-bit floating-point input.

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Compute optimization mechanism

A method of embodiments, as described herein, includes detecting thread groups relating to machine learning associated with one or more processing devices. The method may further include facilitating barrier synchronization of the thread groups across multiple dies such that each thread in a thread group is scheduled across a set of compute elements associated with the multiple dies, where each die represents a processing device of the one or more processing devices, the processing device including a graphics processor.

Barriers and synchronization for machine learning at autonomous machines

One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

Graphics neural network processor, method, and system

Growing community of inventors

Portland, OR, United States of America

John Charles Weast