Polar Semiconductor, Inc.

Polarfab, LLC

John Charles Beckman

Noel P Hoilien

Gregory Allen Michaelson

Steve Kosier

Sandhya Gupta

John P Curcio

Joel Frederick Kluender

A method for generating a layout of a semiconductor circuit to satisfy minimum spacing requirements that includes generating one or more polygons for the layout, with each generated polygon having an area, a plurality of corners and satisfying the minimum spacing requirements of the layout rules. The corners of the generated polygon are then chamfered, and the generated polygon with chamfered corners is expanded or reduced in size.

Method for generating layouts by chamfering corners of polygons

A photodiode array includes a first photodiode and at least a second photodiode. The first photodiode includes a first active area, a first anti-reflective coating area, and a first residual polysilicon ring. The first anti-reflective coating area and the first residual polysilicon ring are formed asymmetrically over the first active area. The second photodiode includes a second active area, a second anti-reflective coating area, and a second residual polysilicon ring. The second anti-reflective coating area and the second residual polysilicon ring are formed asymmetrically over the second active area. The first anti-reflective coating area is formed over a region of the first active region adjacent to the second photodiode, and the second anti-reflective coating area is formed over a region of the second active region adjacent to the first photodiode.

Photodiode array having reduced dead space

A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device is disclosed. The method allows a customer to create a partial layout of the semiconductor device based on a first set of rules, and then allows a manufacturer to generate a more complete layout of the semiconductor device based on the partial layout and the second set of rules.

System and method for defining semiconductor device layout parameters

An integrated circuit having very low parasitic current gain includes a guard ring that is used to completely surround a device, such as a power device, that induces parasitic current. The guard ring is formed in a semiconductor body layer such as an epitaxial layer and has a central guard ring of the same type conductivity as that of the body layer and additional flanking rings of the opposite type conductivity. An unbiased configuration of the guard ring based on the above structure is particularly effective in reducing the parasitic gain. The effectiveness of the guard ring, such as the high current performance, is further improved by reducing the resistance between neighboring rings using various methods.

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Minneapolis, MN, United States of America

John Charles Beckman