Teledyne Scientific and Imaging, LLC

Teledyne Licensing, LLC

John C Stevens

Stefan Clemens Lauxtermann

Adam Lee

Atul Joshi

William E Tennant

Selim Eminoglu

Angelika Kononenko

David J Chiaverini

Gananath Wijeratne

Embodiments of a read-out integrated circuit (ROIC) include a plurality of unit cells. Each unit cell includes a bias subsystem, a reset switch, at least one integration capacitor, and at least one read switch. A focal plane array includes a plurality of photo detectors disposed in a grid and a ROIC. A column buffer includes a first buffer subsystem, a feedback subsystem, a first and second correlated double sampling subsystem, and a second buffer subsystem. A ROIC includes at least one integration subsystem having a transistor subsection, a poly silicon layer, and a plurality of active layer sections.

Multi-color read-out integrated circuit

A correlated double sampling circuit and method for providing the same are disclosed. The circuit may include an amplifier, a plurality of capacitors, and a switch matrix. The amplifier provides a reset voltage replica and a signal voltage replica. The switch matrix controls a plurality of switches to perform correlated double sampling over at least three phases. The first phase for sampling the reset voltage replica on a first and second capacitors. The second phase for sampling the reset voltage replica and the kTC noise on a third capacitor. The first phase producing a thermal kTC noise from the first and second capacitors. The third phase for subtracting a charge representing the signal voltage replica, the kTC noise and the reset voltage replica, combined, from the charge sampled in the second phase to provide an output voltage. The method for providing low noise correlated double sampling includes controlling the plurality of switches to provide the at least three phases.

Low noise correlated double sampling amplifier for 4T technology

An imaging system includes a row and column array of active pixels, each having an associated pitch. In response to respective control signals, each pixel outputs a reset level which includes noise components, or a signal level which includes signal and noise components. Multiple column buffers, each having a pitch equal to or less than that of a pixel, convey the outputs of respective pixel columns to a bus line. Each buffer comprises 'odd' and 'even' S&H/CDS circuits, which process the pixel outputs of odd and even rows, respectively. Each S&H/CDS circuit subtracts pixel reset level from signal level to produce an output in which correlated noise is suppressed. Each column buffer includes a buffer amplifier which conveys the output to the bus line. A gain amplifier separate from the column buffers is coupled to the bus line such that it amplifies the outputs of a multiple column buffers.

Imaging system with low noise pixel array column buffer

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Northridge, CA, United States of America

John C Stevens