International Business Machines Corporation

Sr Technologies, Inc.

John C Sinibaldi

Baiju Dhirajlal Mandalia

Lawrence P Andrews

Gordon Taylor Davis

Judith Marie Linger

Gary L Turbeville

Robert Chih-Tsin Eng

Kevin Bradley Williams

Himanshu Chandrakant Parikh

Oscar E Ortega

Joseph C Petty, Jr

Richard Clyde Beckman

William M Zevin

William R Robinson, Jr

Veerbhadra S Kulkarni

David A Frye

Derrick L Arias

Stephen Rocco Carsello

Laurence Victor Marks

Conrad C Smith

Robert E Landa

Willie James Johnson

Joe Fletcher Jones, Jr

Adam Ruan

Robert A Pebly

Christopher D Touch

Karl-Heinz Ziegenhain

Michael George Ho-Lung

Kevin Lee Graves

Lee H House

Caryn Chan

A method for detection of an orthogonal frequency division multiplex (OFDM) packet preamble is described. The method includes quantizing a real part and an imaginary part of each complex template value to a template index value, determining a plurality of non-zero template index values based on the quantization, receiving a signal including a plurality of samples, performing a plurality of first sums, where each first sum sums a sample subset of plurality of sample subsets, and assigning the plurality of non-zero template index values to the plurality of first sums. The method further includes performing a transposition of each first sum using the assigned non-zero template index value, performing a second sum, where the second sum is a complex weighted sum of the transposition of each first sum, and determining that the received signal comprises the OFDM packet preamble based on the complex weighed sum.

Orthogonal frequency division multiplex packet detection using the long preamble

A method and waveform handling apparatus for capturing and storing data waveforms and metadata for analysis. The method includes receiving waveform data and metadata, the waveform data corresponding to a demodulated data burst, creating a waveform data record from the received waveform data, associating the waveform data with corresponding metadata, and creating a metadata record from the corresponding metadata. The method allows the waveform data in the waveform data record to be stored in a first data repository and the corresponding metadata in the metadata record to be stored in a second data repository, the waveform data and the corresponding metadata accessible for analysis.

System and method for remote waveform analysis with associated metadata

A method and wireless communication device for tracking frequencies of transmitted burst signals. The method includes receiving a burst signal, determining a quality of the burst signal and a carrier frequency of the burst signal, demodulating the burst signal based upon the determined carrier frequency, determining a frequency offset of the burst signal based on the determined carrier frequency, and when the quality of the burst signal exceeds a threshold, calculating a drift window based on the determined frequency offset.

Adaptive frequency tracking mechanism for burst transmission reception

A communication system ( ) includes at least one digital signal processor (DSP) and a WAN driver ( ) operating on a processor that is electrically coupled to a memory. The WAN driver ( ) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated.

Multi-purpose WAN driver for DSP resource adapter

A communication system ( ) includes at least one digital signal processor (DSP) and a WAN driver ( ) operating on a processor that is electrically coupled to a memory. The WAN driver ( ) receives task allocation requests from a host to open/close communication channels that are handled by the at least one DSP. Each task is allocated to one of the at least one DSP according to a total current task processing load for each of the at least one DSP, a maximum processing capability for each of the at least one DSP, and a processing requirement for each task being allocated to the one of the at least one DSP that can handle the additional processing load of the task being allocated. A configuration controller ( ) keeps track of the MIPs processing requirement of each task available for allocation across the plurality of DSPs and the maximum processing capability of each DSP of the plurality of DSPs in response to changes in configuration of the communication system ( ).

Adaptive method and apparatus for allocation of DSP resources in a communication system

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Apparatus including a host processor and communications adapters interconnected with a bus

A remote network server includes primary and secondary routers, each of which include means for emulating a number of different modem types, and for operating in accordance with a number of different communication protocols. Incoming calls are directed at the primary router, but are routed through the secondary router if either the type of modem making a call cannot be emulated in the primary router or if the primary router cannot operate with the protocol used by this calling modem.

Intelligent router for remote internet access

A communications adapter card provides an interface for a TI or E1 transmission line and a signal processing circuit which can be programmed to process receive and transmit data in either an ISDN or an ATM format. Preferably, two such interfaces and two such signal processing circuits are provided on the card, so that a single adapter card can be used for attachment to both an ISDN network and to an ATM network. Each signal processing circuit includes a pair of DSPs, each of which has a two port buffer extending to a parallel bus. All such DSPs are connected to a data bus. The DSPs in each signal processing circuit execute programs to operate in either an ATM mode or an ISDN mode.

Communications adapter for processing ATM and ISDN data

The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.

Multi-speed DSP kernel and clock mechanism

Apparatus including a host processor and communications adapters

A pulse code modulation (PCM) unit is connected to a bus in a computer system. Also, connected to the bus is a processor and memory. The PCM unit is connected to transmit and receive telephone lines. The PCM unit reads uncompressed PCM data from the memory over the bus and compresses the PCM data for transmission over the telephone line in a cycle steal operation, wherein the bus is not being used by the processor. The PCM receives compressed PCM data from the receive telephone line, decompresses it, and writes the decompressed PCM data to the memory in a cycle steal operation. In addition, selectivity of either .mu.-Law or A-Law conversion, selectivity of even bit inversion for A-Law conversion, and selectivity between the compressed/decompressed PCM data or raw data is provided on a per channel basis. Selectable linear gain is also provided.

Pulse code modulation compression mechanism

In an communication system including a computer system comprising a digital signal processing adapter for performing a-set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.

Expandable local inter-system bus architecture in a multiplexed

A digital signal processing system includes a first and second memory coupled to first and second register banks respectively. The system further includes first and second multipliers coupled to the first and second register banks for producing first and second product outputs respectively. The system also includes an arithmetic logic unit having first, second and third inputs and an output. The first input is coupled to the first product output and the second and third inputs are selectively coupled to either of the second product output and the first and second register means. The arithmetic logic unit output is coupled to the first and second register banks for accumulating the sample values in the first and second register banks. The system further includes Instruction control for storing a plurality of instruction op codes and controlling the system to compute the sample values by performing simplex operations during each cycle of a plurality of operating cycles of a digital signal processing procedure.

Digital signal processing system with dual memory structures for

There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block. Upon the completion of performing a DMA request, the DAU will set a complete bit in the control block in the remote processor's memory. An interrupt can also be sent to the CPU, wherein the CPU is advised that a DMA request has been completed. The data in a DMA operation is sent in bursts to a buffer located between two busses having different data transmission rates.

Direct memory access unit for transferring data between processor

A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.

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Pompano Beach, FL, United States of America

John C Sinibaldi