Sun Microsystems, Inc.

John C Schell

David C Banks

Tai Quan

Teshager Tesfaye

Kin M Ho

Matthew J Tedone

Kenneth A Schmahl

Drew George Doblar

Ebrahim Hashemi

Christian Cadieux

Stephen A Wiley

James M Byrd

Alex Umino

Ray P Chan

Igor Karminsky

Manuel Cisneros

A system for a distributed computing network for managing instrumentation information from a plurality of network-connected managed entities. One or more instrumentation processes are coupled to each of the network-connected managed entities and configured to gather performance metric values. A first classification process is responsive to information describing a type of input/output operation being performed and is configured to select one or more counters based upon the type of input/output operation being performed. A second classification process is coupled to receive a performance metric value from the one or more instrumentation processes. The second classification process is responsive to a computed logarithm of a measured value of at least one metric to select and increment a particular counter of the one or more counters selected by the first classification process.

Cost efficient performance statistics gathering using logarithmic indexing

A fault isolation system in a network is disclosed, particularly suited for use in a unidirectional fibre channel arbitrated loop. Information relating to read and write errors occurring on the loop is stored, and fault regions are located by determining areas on the loop downstream of write errors and upstream of read errors. The system may be extended to networks with bidirectional communications by storing directionality information with the detected errors. Command and response error information is not needed to deterministically locate the fault regions. When a given fault region is identified, loop and device diagnostics are executed for that region of the loop to specifically identify the failed components.

System and method for isolating faults in a network

A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe. Multiple erasure correction is also contemplated.

Storage array having multiple erasure correction and sub-stripe writing

A method for automatically arbitrating for mastership of a fiber channel loop in a host adapter circuit configured for coupling a host electronic device with the fiber channel loop. The host adapter circuit has a processor and a loop control circuit different from the processor. The loop control circuit is coupled to a memory of the host adapter circuit. The method includes sending out a host ARBITRATE primitive on the fiber channel loop. The method further includes employing the loop control circuit to monitor received ARBITRATE primitives received at the host adapter circuit from the fiber channel loop. There is also included ascertaining, using the loop control circuit, whether one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously. If the one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously, the method includes placing a target device coupled to the fiber channel loop in an OPENED state for receiving data from the host electronic device.

Fiber channel automatic arbitration and communication control

A method, in a host adapter circuit configured for coupling a host electronic device with one of a fiber channel loop and a point-to-point communication channel, for receiving data at the host adapter circuit from one of the fiber channel loop and the point-to-point communication channel. The method includes providing a selectable control signal configured for indicating whether the host adapter circuit is coupled to the fiber channel loop or the point-to-point communication channel. The method further includes providing a front-end receive circuit. The front-end receive circuit is configured for coupling with an input data port. The input data port represents one of the fiber channel loop and the point-to-point communication channel. The method also includes coupling the front-end receive circuit with the selectable control signal. Additionally, the method includes coupling an output of the front-end receive circuit with a decoder of the host adapter circuit, wherein the front-end receive circuit is configured to process, responsive to the selectable control signal, either fiber channel loop data from the fiber channel loop or point-to-point data from the point-to-point communication channel from the input data port to provide parallel data having a predefined size to the decoder circuit.

Communication controllers and methods therefor

A method for passing mastership of a bus is described. According to the method, it is determined whether to use the bus. If the bus is to be used, it is determined whether the bus is available. If the bus is available, the bus is accessed and a signal is generated to indicate that the bus is being accessed. A timer is also started and access to the bus is yielded when the timer expires. A processor that passes mastership to a shared resource is also described. The processor comprises a resource accessing unit. The resource accessing unit allows the processor to access a resource upon receiving a first signal from a component coupled to the resource. The resource accessing unit yields access of the resource to the component upon receiving a second signal from the component.

Growing community of inventors

Westminster, CO, United States of America

John C Schell