Tensilica, Inc.

Cadence Design Systems, Inc.

Radiance Technologies, Inc.

John C Ruttenberg

Walter David Lichtenstein

Christopher Rowen

Earl A Killian

Ricardo E Gonzalez

Robert P Wilson

Monica Lam

Ashish B Dixit

Albert Ren-Rui Wang

Dror E Maydan

Fouad A Tobagi

David Lemke

David Agraz

Ashfaq A Munshi

Dror Eliezer Maydan

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

System and method of designing instruction extensions to supplement an existing processor instruction set architecture

System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions

Automated processor generation system for designing a configurable processor and method for the same

A system and method for scheduling transfers of data through a network, the system comprising a transfer module at each node in the network, the transfer module being configured to schedule data transfers according to available resources at each node. In one embodiment, the transfer module includes a scheduling module, a routing module, and an execution module. The scheduling module at each node evaluates a single hop request in view of objectives, such as a deadline, and the available resources at that node, for example transmit bandwidth, receive bandwidth, and storage space, all of which may change as a function of time.

System and method for scheduling and executing data transfers over a network

A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S&equals;IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.

High data density RISC processor

Growing community of inventors

Newton, MA, United States of America

John C Ruttenberg