Motorola Corporation

Asset Intertech, Inc.

Southern Methodist University

Advantest (singapore) Pte Ltd

John C Potter

Alfred Larry Crouch

Michael Alan Mateja

Richard C Dokken

Gerald Chan

Jennifer Lynn Dworak

Adam Zygmontowicz

Various integrated circuits protect hidden content e.g., embedded instruments, keys, data, etc.) using scan cell circuit(s). For example, a first scan cell circuit is connected to the hidden content, and a second scan cell circuit is connected to the first scan cell circuit forming all or part of a serial data path. The first scan cell circuit provides access to the hidden content whenever the first scan cell circuit is in a first specified state and prevents access whenever the first scan cell circuit is in a different state. The first scan cell circuit does not interrupt the serial data path when the first scan cell circuit is in the different state. The second scan cell circuit changes an operational characteristic of the first scan cell circuit whenever the second scan cell circuit is in a second specified state. In some cases, the second scan cell circuit can be eliminated.

Protecting hidden content in integrated circuits

A network of storage units has a data path which is at least a portion of the network. The network also has a key storage unit and a gateway storage unit. If the key storage unit stores a key value, the key storage unit transmits a key signal to the gateway storage unit. If the gateway storage unit does not store a gateway value or the key signal is not transmitted to the gateway storage unit, the gateway storage unit does not insert a data path segment in the data path. If the gateway storage unit stores a gateway value and the key signal is transmitted to the gateway storage unit, the gateway storage unit inserts the data path segment.

Protection of proprietary embedded instruments

A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Process for improving design-limited yield by localizing potential faults from production test data

A method of testing a logic device that includes the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device ( ), converting the first test vector from an input pin format into state data associated with the logic device ( ), and searching the internal state data to identify a set of last shift transitions ( ). A method of making a logic device having a specification frequency, the method including the steps of providing an integrated circuit, testing the integrated circuit using a scan test pattern at a frequency at least as great as the specification frequency ( ), performing a diagnosis procedure to produce a diagnosis result ( ), and producing the integrated circuit in a final form after the diagnosis result indicates a non-functional problem ( ). The diagnosis result indicates at least one of a non-functional problem and a speed problem.

Method of making logic devices

A method of testing a logic device that includes the steps of identifying a first test vector corresponding to a test failure resulting from testing of the logic device (10), converting the first test vector from an input pin format into state data associated with the logic device, and searching the internal state data to identify a set of last shift transitions. A method of making a logic device having a specification frequency, the method including the steps of providing an integrated circuit, testing the integrated circuit using a scan test pattern at a frequency at least as great as the specification frequency, performing a diagnosis procedure to produce a diagnosis result, and producing the integrated circuit in a final form after the diagnosis result indicates a non-functional problem. The diagnosis result indicates at least one of a non-functional problem and a speed problem.

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Austin, TX, United States of America

John C Potter