Synaptics Corporation

John C Platt

Carver A Mead

Janeen D Anderson

Michael F Wall

Nada P Matic

Timothy P Allen

Chung-Ning Wang

Glenn E Gribble

Richard Robert Schediwy

Federico Faggin

Steven J Nowlan

Joseph Decker

Gregory E Leyh

Jeffrey Orion Pritchard

Josef C Frisch

Ting Kao

A method and system are provided for drawing or writing using an input device in computer systems. The system provides an absolute-coordinate drawing mode, in which the user may draw written strokes to which the computer system display is responsive, and a relative-coordinate repositioning mode, in which the user may figuratively &ldquo;pick up the pen&rdquo; and reposition the beginning of a following written stroke. The system enters the drawing mode in response to a user command, and remains in the drawing mode in response to continued written strokes. The system enters the cursor mode after a selected time period occurs with no written strokes, or in response to other user commands. In the drawing mode, a coordinate system for the touchpad is mapped to a coordinate system for a selected window on the display. The mapping is selected so that an initial position of a written stroke in the window corresponds to a final position selected during the cursor mode, so that the user is able to reposition the input device when it has (or is about to) &ldquo;run off the edge&rdquo; of an input tablet which is relatively smaller than the display. The system uses either a resistive touchpad input tablet, or a capacitive touchpad input tablet in conjunction with a passive stylus input device having a flexible conductive writing tip. The system alternatively provides a signature mode, in which the user is able to make a simple drawing, such as a handwritten signature.

Pen drawing computer input device

A method for incremental recognition of ideographic handwriting comprises in order the steps of: (1) entering in a natural stroke order at least one stroke of an ideographic character from a computer entry tablet; (2) providing the at least one stroke to an incremental character recognizer, which produces a hypothesis list of at least one candidate character; (3) displaying a hypothesis list of candidate characters containing the at least one stroke; (4) selecting a correct character from among the candidate characters on the hypothesis list if it a correct character appears thereon; (5) entering in natural stroke order at least one additional stroke of the ideographic character from the computer entry tablet if no candidate character is a correct character; (6) providing the additional stroke(s) to the incremental character recognizer, which produces an updated hypothesis list; (7) displaying the updated hypothesis list of candidate characters containing every stroke; (8) selecting a correct character from among the candidate characters on the updated hypothesis list if it a correct character appears thereon; and (9) repeating steps (5) through (8) until a correct character is selected from the updated hypothesis list.

Incremental ideographic character input method

A method for incremental recognition of ideographic handwriting comprises in order the steps of: (1) entering in a natural stroke order at least one stroke of an ideographic character from a coordinate entry tablet; (2) providing the at least one stroke to an incremental character recognizer, which produces a hypothesis list of at least one candidate character; (3) displaying a hypothesis list of candidate characters containing the at least one stroke; (4) selecting a correct character from among the candidate characters on the hypothesis list if it a correct character appears thereon; (5) entering in natural stroke order at least one additional stroke of the ideographic character from the coordinate entry tablet if no candidate character is a correct character; (6) providing the additional stroke(s) to the incremental character recognizer, which produces an updated hypothesis list; (7) displaying the updated hypothesis list of candidate characters containing every stroke; (8) selecting a correct character from among the candidate characters on the updated hypothesis list if a correct character appears thereon; and (9) repeating steps (5) through (8) until a correct character is selected from the updated hypothesis list.

An object proximity sensor includes a capacitive touch-sensitive transducer including row conductive lines insulated from column conductive lines to from a matrix. An insulating layer is disposed over the matrix and has a thickness selected to achieve significant capacitive coupling between an object placed on its surface and the matrix. Circuitry first drives each of the row conductive lines to a fixed voltage and then simultaneously injects a known amount of charge onto each of the row conductive lines, and then senses for each row conductive line a row-sense voltage created by the known amount of charge injected onto each of the row conductive lines, and, simultaneous with injected the known amount of charge, changes the voltage on all of the column conductive lines in the same direction as the row-sense voltage by an amount no greater than about twice the difference between the fixed voltage and an average of all row-sense voltage in the transducer. Circuitry first drives each of the column conductive lines to a fixed voltage and then simultaneously injects a known amount of charge onto each of the column conductive lines, and then senses for each column conductive line a column-sense voltage created by the known amount of charge injected onto each of the column conductive lines, and, simultaneous with injecting the known amount of charge, changes the voltage on all of the row conductive lines in the same direction as the column-sense voltages by an amount no greater than about twice the difference between the fixed voltage and an average of all column-sense voltages in the transducer. A set of object-sensed electrical signals related to all of the row-sense voltages and all of the column-sense voltages is produced.

Object position detector

A force sensing touchpad comprises a substantially rigid touch surface; a substantially rigid frame; a plurality of spring structures formed integrally with the touch surface and mechanically connected to the reference frame; and a circuit for deriving force information from capacitances proportional to the distances between predetermined portions of the touch surface and portions of the frame in response to a force applied to the touch surfaces.

Force sensing touchpad

A system for recognizing handwritten characters, including pre-processing apparatus for generating a set of features for each handwritten character, a neural network disposed for operating on sparse data structures of those features and generating a set of confidence values for each possible character symbol which might correspond to the handwritten character, and post-processing apparatus for adjusting those confidence values and for selecting a character symbol consistent with external knowledge about handwritten characters and the language they are written in. The pre-processing apparatus scales and re-parameterizes the handwritten strokes, encodes the scaled and re-parameterizd strokes into fuzzy membership vectors and binary pointwise data, and combines the vectors and data into a sparse data structure of features. The (nonconvolutional) neural network performs a matrix-vector multiply on the sparse data structure, using only the data for nonzero features collected in that structure, and, for a first layer of that neural network, using only successive chunks of the neural weights. The post-processing apparatus adjusts the confidence values for character symbols using a set of expert rules embodying common-sense knowledge, from which it generates a set of character probabilities for each character position; these character probabilities are combined with a Markov model of character sequence transitions and a dictionary of known words, to produce a final work output for a sequence of handwritten characters.

Handwriting recognition system and method

A two-layer network according to the present invention is comprised of a first-layer array of electrically-adaptable synaptic elements, inter-layer connection circuitry comprised of electrically adaptable elements, and a second-layer array of electrically-adaptable synaptic elements. Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor in each electrically adaptable element, usually comprising the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. Each synaptic element in the synaptic array comprises an adaptable CMOS inverter or other amplifier circuit. The inputs to all first-layer synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The outputs of all first layer synaptic elements in a column are connected to a common sense amplifier on a sense line. The outputs of the sense amplifiers are connected to the inputs of the synaptic elements of the second layer of the array. The outputs of all synaptic elements in a given row in the second layer of the array are connected to a common row output line. In order to adapt the synaptic elements in the array, the voltages to which the synaptic elements in a given column of the first layer of the array is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for the column. The voltages to which the synaptic elements of the second layer of the array are to be adapted are placed on the row outputs lines.

Two layer neural network comprised of neurons with improved input range

A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.

Electrically adaptable neural network with post-processing circuitry

A continuous weight-update device for a synaptic element including at least one MOS transistor comprises a floating node having a capacitance associated therewith, the floating gate comprising at least a part of the floating node, first and second input lines, first and second error lines, an electron tunneling structure coupled to the floating node for tunneling electrons from the floating node, and an electron injecting structure coupled to the floating node for injecting electrons onto the floating node. Control circuitry is responsive to signals on the first input and error lines, for activating the electron tunneling structure, and control circuitry is responsive to signals on the second input and error lines, for activating the electron injecting structure. Circuitry is provided for driving signals onto the first and second input and error lines. Both a single synapse and an array of synapses incorporating the continuous weight-update device are also taught.

Continuous synaptic weight update mechanism

A weight-storage and weight-adjustment circuit includes a first hot electron injection device coupled to a first floating gate and a second hot electron injection device coupled to the second floating gate. The floating gates are associated with two series connected MOS transistors. The first and second hot electron injection devices comprise gated lateral bipolar transistors. The weight may be decreased by injecting hot electrons from the first hot electron injection device onto the first floating gate to decrease the first analog voltage and increased by injecting electrons from the second hot electron injection device onto the second floating gate to decrease the second analog voltage. Circuitry are provided to periodically adjust the absolute voltage levels on the first and second floating gates to prevent them from becoming too negative over time. First and second electron tunneling devices are coupled to the first and second floating gates, respectively, to simultaneously adjust the voltages stored on the floating gates to keep them within a desired voltage range.

Synaptic element including weight-storage and weight-adjustment circuit

A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.

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Mountain View, CA, United States of America

John C Platt