International Business Machines Corporation

John C O'Quin, Iii

John Thomas O'Quin, Ii

James O Nicholson

Albert Y Chang

Frederick E Strietelmeier

Mark D Rogers

Stephen P Morgan

Todd A Smith

Marc Alan Auslander

Mark F Mergen

Richard G Fogg, Jr

Keith E Duvall

Arturo M De Nicolas

George A Lerom

Anthony D Hooten

Arturo M De Nicholas

A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

I/O cache controller containing a buffer memory partitioned into lines

A computer system has a cache located between input/output devices and a main system memory. All system memory accesses by the input/output devices are made through the cache. Memory accesses through the cache are limited to those addresses which are accessible to a central processor and input/output devices. All access to such addresses by the central processor are made through the cache.

Computer system with input/output cache

The system and method of this invention simulates the flow of control of an application program targeted for a specific instruction set of a specific processor by utilizing a simulator running on a second processing system having a second processor with a different instruction set. The simulator reduces the number of translated instructions needed to simulate the flow of control of the first processor instructions when translating the address of the next executable instruction resulting from a dynamic transfer of control, i.e., resulting from a return instruction. The simulator compares the address that is loaded at run time by the return instruction with the return address previously executed by that instruction. If the last return address matches, the location of the return is the same. If the last return does not match, a translate look-aside buffer is used to determine the address. If the translate look-aside buffer does not find the address, then a binary tree look up mechanism is used to determine the address of the next instruction after a return. The performance of the simulator is enhanced by utilizing the easiest approaches first in the chance that a translated instruction will result most efficiently.

Translating a dynamic transfer control instruction address in a

A data processing method for storing groups of related information in a storage subsystem of a data processing system in which the storage subsystem includes one or more storage devices having a plurality of block addressable storage locations (blocks or sectors) each of which stores a predetermined fixed number of bytes of said information. The method includes the step of establishing allocatable increments of storage, called physical partitions, which comprise a predetermined number of contiguous addressable blocks, and initially allocating, in response to a request to the operating system, a preselected number of partitions for each group of related information, where the partitions in each group are not necessarily physically contiguous and where the number that is selected is the minimum number of partitions required to store the group of related information. The method further includes the step of automatically allocating one or more additional partitions, located physically on any device, to a previously allocated group of related partitions, dynamically in response to another request of the operating system. A group of partitions that have been allocated to store a group of related information, such as individual files that are related in a hierarchical file system, is called a 'Logical Volume'. Logical Volumes may be further combined for administration and data management reasons into a 'Volume Group'.

Data processing method to create virtual disks from non-contiguous

The system and method of this invention allows a simulated processor to receive an interrupt request from I/O devices. A simulated interrupt controller routine determines whether to post an interrupt to the simulated CPU. The simulated interrupt controller routine posts an interrupt to the simulated CPU by updating one byte, which is owned by the simulated interrupt controller, of a two byte halfword. The other byte is owned by the simulated CPU and is updated by the simulated CPU when its internal interrupt enabled state changes. Each byte of the two byte halfword is updated independently, but is loaded by the simulated CPU with only one instruction to determine if an interrupt should be acknowledged. The simulated CPU minimizes the overhead of polling for an interrupt by performing a graph analysis of the instruction flow of control to determine the locations to poll for interrupts. The simulated CPU polls for an interrupt when an instruction transfers control dynamically, once around a loop, and when an instruction changes the interrupt enabled state of the simulated CPU.

System and method for simulating the I/O of a processing system

A memory management system method increases the size of a segment in blocks of 64K virtual pages in response to the system detecting that the requested page has been protected. The conventional UNIX type System Calls create and open files in virtual memory. All pages are protected 'read only' until a SHMAT type System Call is made to operate on a page at a specific address. At that point in the process, a protection exception is recognized by the system and the UNIX kernel takes control to remove the protection and update the appropriate data structures to reflect the new status of the page and the addresses in real memory where the page may be found. Segments containing mapped files are also extended by the method.

Method to automatically increase the segment size of unix files in a

A method for use in a virtual memory data processing system employing a pageable External Page Table data structure for recording current status and disk address information for each virtual page in said system, provides improved system performance when a large number of virtual pages are to be operated on in the same manner. In accordance with the method, each page of External Page Table entries can record a predetermined number of entries (512), depending on the byte capacity of each virtual page (2,048) and the size of each entry (4 bytes). One page of 512 entries correspond to 1 megabyte of virtual storage (512.times.2,048) and also appears as one entry in a pinned External Page Table. The pinned External Page Table is referred to as the 'XPT of the XPT,' and has the same format as the pageable XPT. A 256 megabyte segment of virtual memory is representable in the XPT of the XPT by 256, 4 byte entries, or one-half of a page. Where all virtual pages represented by a page of XPT entries are to be processed in the same way (i.e., created, destroyed), one operation on one entry in the XPT of the XPT is made, rather than 512 operations on the 512 entries of the XPT.

Method to operate on large segments of data in a virtual memory data

A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.

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Austin, TX, United States of America

John C O'Quin, Iii