Vanguard International Semiconductor Corporation

John C Lin

Meng-Jaw Cherng

Daniel Hao-Tien Lee

A method for manufacturing an array of dynamic random access memory (DRAM) cells having a single crown-shaped or a double crown-shaped stacked capacitors is accomplished. The method involves forming an array of device areas on a silicon substrate in which FETs for the DRAM cells are formed. After forming bit line contacts and bit line metallurgy contacting one of the two source/drain areas of each FET, a thick low melting temperature glass (BPSG) is deposited and planarized by annealing. Node capacitor contact openings are formed in the BPSG using a polysilicon sidewall method that reduces the contact size, and a thick polysilicon layer is deposited to contact the node source/drain areas of the FETs, and also provides a planar polysilicon surface. A specially designed edge phase-shift mask is then used with a positive photoresist to pattern the thick polysilicon layer and form crown-shaped bottom electrodes. The capacitors are then completed by depositing a interelectrode dielectric and forming a polysilicon top electrode. A second phase-shift mask design is used to form a double crown-shaped capacitor. These new capacitors are estimated to increase the capacitance over the more conventional thick capacitor by about 50 and 115%, respectively.

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Hsin-chu, Taiwan

John C Lin