Silicon Graphics, Incorporated

John C Lin

Peter R Birch

Robert Allen Shaw

Philip R Manela

Daniel R Ullum

Michael B Nagy

A method is used to access a sub-region of a two or more dimensional data region, in which said region is composed of a patchwork of individually addressable tiles. A hardware assisted mechanism is used to address, reformat, and composite data from each tile to produce a row-major subregion data stream to the consuming device. This method abstracts information about how the desired region is stored and addressed, so that further processing steps can process the data as a contiguous two or more dimensional space without regard to how the data is composited. This is particularly useful for doing image processing on graphics processing systems where source data is often stored in separately managed and addressed tiles.

Apparatus and method for accelerated tiled data retrieval

A method of gaining access to multiple signals internal to a semiconductor chip while minimizing the number of pins dedicated for diagnostic and testing purposes. A chip designer determines which internal signals would most likely be helpful in troubleshooting and debugging a new chip design. These signals are input to a selector. A configuration register is loaded with information specifying which ones of these signals is to be routed to the output pin(s) so that they can be monitored externally by a logic analyzer in real-time. The selector only routes the currently designated signals to the appropriate output pin(s). Subsequently, a different set of signals can be selectively routed to the output pin(s) in place of the originally chosen signals.

Output pin for selectively outputting one of a plurality of signals

A hierarchical display list system and efficient processing method for same. The system provides a display list having discontiguous display list segments and an information retrieval system for same (e.g. DMA controller in one embodiment). Each display list segment (DLS) contains a call to a next to be processed DLS or a return. The call includes a push (which indicates the address of the return DLS) and also a jump control data (which indicates the address of the next to be processed DLS. The push and jump and also contain the length of the respective DLS's involved. DLSs can also contain return control data which include a POP and a jump. Nesting (e.g. the display list control path) is maintained by a display list stack. The discontiguous DLSs are separately stored in memory of the host processor. According to the system, the information for traversing the hierarchical display list is stored in the display list itself so the host processor is not required for display list processing aside from initializing the rendering procedure. In an improvement embodiment, the transfer control information (e.g., call and return) are placed in the front of the DLS so that the information retrieval system can initialize and set up for the control transfer in parallel while the current DLS is processed. This improvement provides faster control transfer between. DLSs and keeps the graphics FIFO substantially filled during the display list rendering process.

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Cupertino, CA, United States of America

John C Lin