Integrated Device Technology, Inc.

Oracle International Corporation

John C Hsu

Alok Kumar Srivastava

Angelo Pruscino

Wilson Wai Chan

Tolga Yurek

Jeffrey Fischer

Deepti Srivastava

Chung-Yu Wu

Hui Henry Li

Tak Fung Wang

Eugene Reddy Ho

Min Chu

Vikas Kumar Agrawal

Yu Kin Ho

Feng Qiu

Cheng Wen Hsiao

Ron Wade

Wei-Ching Chan

Beverly Zane

An apparatus includes a phase locked loop circuit having a phase comparator for generating a signal indicative of a phase difference between a signal presented to a first input of the phase comparator and a signal presented to a second input of the phase comparator. The apparatus includes at least one delay element disposed so as to enable contributing at least one of the following:

Buffer with programmable input/output phase relationship

A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

Frequency synthesizer with microcode control

An integrated circuit includes a low voltage differential signaling (LVDS) output circuit, a high-speed current steering logic (HCSL) output circuit, a bias control circuit, a programmable voltage reference circuit coupled to the bias control circuit, an output stage circuit coupled to the HCSL output circuit, a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit, a second plurality of switches to switchably couple the bias control circuit to the output stage circuit and to the HCSL output circuit and a logic control circuit coupled to the programmable voltage reference circuit, the first plurality of switches and the second plurality of switches. The logic control circuit is configured to activate either the LVDS output circuit or the HCSL output circuit.

Integrated low voltage differential signaling (LVDS) and high-speed current steering logic (HCSL) circuit and method of use

Techniques for adaptive trace logging include, in one embodiment, obtaining input data on trace logging behavior and computing resources used by trace logging. Based on the obtained input data, an adaptive trace logging module automatically takes action at runtime to reduce the amount of computing resources consumed by tracing logging. For example, the action taken may include decreasing a trace logging level of an executing software program to reduce the number of trace logging messages added to a trace log. In another embodiment, the techniques include detecting a condition of an executing software program that warrants a change to a trace logging level of the executing program. The adaptive trace logging module automatically changes the trace logging level of the executing program as-needed for the detected condition. For example, the adaptive trace logging module may increase the trace logging level of an executing program upon detecting a deadlock or other abnormal condition of the executing program. By automatically increasing the trace logging level upon detecting an abnormal condition, additional trace logging messages may be written to a trace log aiding diagnosis and troubleshooting of the condition.

Techniques for adaptive trace logging

The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input.

Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM)

A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for the driver.

Low power driver with programmable output impedance

An output driver is provided that adapts an output impedance of the output driver to the voltage level of a power supply, thereby providing a constant output impedance over a range of different operating voltages. The output driver includes a plurality of individual driver circuits, each one of the plurality of individual driver circuits configured to provide a plurality of predetermined output impedances in response to a plurality of power supply voltage level inputs and a decoder. The decoder of the output driver is configured for receiving a digital codeword representative of a voltage level of a power supply coupled to the output driver and for decoding the digital codeword to activate one or more of the individual driver circuits to provide a constant output impedance from the output driver in response to the voltage level of the power supply coupled to the output driver, wherein the constant output impedance is a combination of the predetermined output impedances of the activated individual driver circuits.

Output driver having output impedance adaptable to supply voltage and method of use

An low voltage differential signaling (LVDS) driver is provide having an output voltage amplitude regulator for regulating an output voltage amplitude of the LVDS driver by receiving a differential output signal from a switched-polarity current generator of the LVDS driver at an output voltage amplitude regulator of the LVDS driver, detecting an output voltage amplitude of the differential output signal, comparing the output voltage amplitude to a reference voltage at the output voltage amplitude regulator and regulating a steering current of the LVDS driver based upon the comparison between the output voltage amplitude and the reference voltage to regulate an amplitude of the differential output signal at one or more loads of the LVDS driver.

Low voltage differential signaling (LVDS) driver with differential output signal amplitude regulation

An integrated circuit is provided that allows for the use of the same supply voltage pin to receive both a normal operating voltage for the integrated circuit (IC) and a one-time-programmable (OTP) memory program voltage sufficient to program an OTP memory located on the integrated circuit. In one embodiment, when an OTP programming voltage is received at a supply voltage pin of the IC, the OTP programming voltage is provided to the OTP memory of the integrated circuit and the OTP programming voltage is regulated to the normal operating voltage level prior to providing the voltage to the internal circuitry of the integrated circuit. As such, the present invention establishes a dual-purpose supply voltage pin, thereby eliminating the need for a separate OTP programming voltage pin on the integrated circuit.

System and method for voltage regulation of one-time-programmable (OTP) memory programming voltage

Described herein are techniques for adaptively managing timers that are used in various layers of a node. In many cases, the number of timers that occur in the system is reduced by proactively and reactively adjusting values of the timers based on conditions affecting the system, thereby making such a system to perform significantly better and more resiliently than otherwise.

Adaptive cluster timer manager

Provided herein is a name service that includes published data that is associated with one or more duration entities and one or more modification entities, enabling the name service to more efficiently manage access to published data. To publish data, a publishing client transmits a publication request to a name service. The publication request may specify a modification entity. The name service creates at least one name entry that associates the published data with the modification entity. There are several types of requests to modify data that a name service will honor only when they originate from a modification entity.

Managing the size and accessibility of a name service

Provided herein is a name service that includes published data that is associated with one or more duration entities and one or more modification entities, enabling the name service to more efficiently manage access to published data. To publish data, a publishing client transmits a publication request to a name service. The publication request may specify a modification entity and a duration entity. The name service creates at least one name entry that associates the published data with the modification entity and the duration entity. There are several requests to modify or depublish published data that a name service will honor only when they originate from a modification entity. These are (1) requests to modify published data, and (2) requests to depublish published data. A name service depublishes published data based on the termination of the duration entity that is associated with the published data, when, for example, a garbage collector detects that the duration of an entity has ended. Name service recovery is performed on a system failure. The remaining name service daemons delete each name entry that is non-local and non-persistant, and transmit requests to replicate local name entries to the other surviving name service daemons. A name service persistently stores name entries as specified. When restarted, the name service may continue to provide the persistently stored name entries. Persistent name entries are not depublished during name service recovery. They are explicitly modified or depublished by a modification entity.

Growing community of inventors

Sunnyvale, CA, United States of America

John C Hsu