Freescale Semiconductor,inc.

Motorola Corporation

Amd Inc.

John C Flake

Kevin Cooper

Yuri Solomentsev

Saifi Usmani

Janos Farkas

Stanley Michael Filipiak

Terry Grant Sparks

Yeong-Jyh Tom Lii

Kathleen C Yu

Kirk J Strozewski

Johannes Groschopf

Bradley P Smith

Cindy K Goldberg

Jennifer Lynn Cooper

Johannes Friedrich Groschopf

A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than &#x2266;200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator.

Process for filling recessed features in a dielectric substrate

A method for processing semiconductor wafers is disclosed. A solution is applied to a semiconductor wafer to prevent dendrites and electrolytic reactions at the surface of metal interconnects. The solution can be applied during a CMP process or during a post CMP cleaning process. The solution may include a surfactant and a corrosion inhibitor. In one embodiment, the concentration of the surfactant in the solution is less than approximately one percent by weight and the concentration of the corrosion inhibitor in the solution is less than approximately one percent by weight. The solution may also include a solvent and a cosolvent. In an alternate embodiment, the solution includes a solvent and a cosolvent without the surfactant and corrosion inhibitor. In one embodiment, the CMP process and post CMP cleaning process can be performed in the presence of light having a wavelength of less than approximately one micron.

Method to passivate conductive surfaces during semiconductor processing

This disclosure describes a low particle concentration formulation for slurry which is particularly useful in continuous CMP polishing of copper layers during semiconductor wafer manufacture. The slurry is characterized by particle concentrations generally less than 2 wt %, and advantageously less than 1 wt %. In particular embodiments, where the particle concentration is in a range of 50 to 450 PPM, an 8-fold increase in polishing rate over reactive liquid slurries has been realized. Slurries thus formulated also achieve a reduction in defectivity and in the variations in planarity from wafer to wafer during manufacture, by improving the stability of polishing quality. The slurry formulations permit substantial cost savings over traditional 2-component, reactive liquid and fixed/bonded abrasive slurries. In addition the formulations provides an advantageous way during CMP to easily change the selectivity or rate of removal of one film material vs. another. Yet another use is to provide slurry 'pulsing' as a means to activate bonded abrasive or fixed abrasive slurry technology.

CMP metal polishing slurry and process with reduced solids concentration

A method for processing semiconductor wafers is disclosed. A semiconductor wafer is provided to a semiconductor processing stage where a block copolymer surfactant (BCS) is applied to the wafer surface. In one embodiment, the BCS includes a hydrophobic portion and a hydrophilic portion. Alternatively, the BCS may be a silicone-containing BCS. In one embodiment, the BCS is within an aqueous solution where the concentration of the BCS within the aqueous solution is less than one percent by weight. Also disclosed is an aqueous solution including abrasive particles and a BCS having a hydrophobic portion and a hydrophilic portion. The abrasive particles may include silica, alumina, or ceria.

Method of using an aqueous solution and composition thereof

Dummy features () are formed within an interlevel dielectric layer (). Passivation layers (and) are formed by electroless deposition to protect the underlying conductive regions (and) from being penetrated from the air gaps (). In addition, the passivation layers (and) overhang the underlying conductive regions (and), thereby defining dummy features (and) adjacent the conductive regions (and). The passivation layers (and) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.

Method for forming a passivation layer for air gap formation

Growing community of inventors

Montbonnot, France

John C Flake