Vlsi Technology, Inc.

Philips Electronics North America Corporation

Marvell International Limited

Semiconductor Components Industries, LLC

Acoustic Technologies, Inc.

Vsli Technology, Inc.

John C Ciccone

Thomas Ciccone

Paul S Levy

Richard David Taylor

Samuel L Thomasson

D C Sessions

Bryan Wayne McCoy

Carl F Liepold

Thomas Duffy

Dc Sessions

Yongyut Yuenyongsgool

Stephen David Nemetz

Timothy Kaske

Bing L Yup

Charles Robert Rimpo

A semiconductor component that includes a current limit circuit and a method for limiting current in the semiconductor component. An input/output pin is connected to the gate of a transistor and a control resistor is connected between the gate of the transistor and its source. One terminal of the control resistor is connected to the input/output pin and the other terminal is connected to another input/output pin. A current source is connected to the input/output pin. A reference voltage is generated between the two input/output pins and compared with a drain-source voltage that is between one of the two input/output pins and another input/output pin. A control voltage is set in accordance with the comparison. The control voltage then controls the voltage on another of the pins that is not common to the reference voltage and to the drain-source voltage.

Method for limiting current and circuit therefor

A numerically controlled oscillator (NCO) is arranged to accumulate control values for each transition of a system clock to provide an accumulation signal and an edge signal. A speed multiplier value (N) is selected to simulate a desired clock resolution of N times the system clock resolution. The multi-phase predictive clock circuit is arranged to provide clock phase output signals that each correspond to a predicted clock phase as if the system clock where running at N times faster than the actual system clock. The edge detector circuit is arranged to compare values of adjacent clock phases to identify a transition in one of the clock phases. The phase encoder circuit is arranged to provide a phase signal that indicates a transition in one clock phase. The edge signal and the phase signal can be used for careful phase alignment control at effectively higher resolution.

Numerically controlled oscillator

Data is transferred by delaying an audio signal less than fifty milliseconds to produce a shadow signal and combining the shadow signal with the audio signal. The shadow represents the data to be transferred A telephone constructed in accordance with the invention has at least two, separate machine states, each of which includes operating in half duplex mode and two, separate machine states, each of which includes operating in full duplex mode. The state is selected based upon one or more shadows detected at the line input of the telephone.

Background communication using shadow of audio signal

A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent. A method is also provided.

5-ary receiver utilizing common mode insensitive differential offset comparator

A method of designing a reset circuit for a digital integrated circuit (IC) layout is described. The reset circuit is designed with the intention of making it visually non-detectable in the digital IC layout by implementing the reset circuit entirely in digital elements and then using standardized digital layout cells and routing such that the reset circuit is essentially non-discernible from the digital circuitry of the IC device layout. In addition, circuit elements are designed using devices having dimensions that are essentially the same as typical digital devices in the digital IC layout.

Standard cell power-on-reset circuit

A system for performing high speed exponentiation in a secure environment. The system includes an interface for receiving encrypted data sent from a host system, a plurality of exponentiators capable of operating concurrently, an encyptor decrypting data received from a host system and encrypting data produced from the exponentiators, and logic circuitry for selecting an available and properly functioning exponentiator to perform exponentiation on the received data.

Secure cryptographic multi-exponentiation method and coprocessor

A single-ended power supply under-voltage level detection circuit included first and second stages of devices stacks coupled between a power supply signal and a reference potential. As the power supply increases it overcomes device threshold voltages in the first stage causing it to enable the second stage. As the power supply signal continues to increase and reaches a second voltage level, the second stage outputs a level indicator signal which indicates that the power supply is greater than or equal to a predetermined voltage level. A power-down signal can be externally applied to devices in the first and second stages so as to disable the detection circuit no matter what the power supply signal level is. In addition, the detection circuit can be used in a power-on-reset (POR) circuit to detect when the power supply has reached a predetermined voltage level so as to cause the POR circuit to output a POR signal an extended time interval afterwards.

Low power undervoltage detector with power down mode

A differential true single phase latch and flip-flop designed to embody logic functions is described. The logic function embodied latch includes a first circuit branch including first input switching devices for receiving a first set of input signals which include input signals and their corresponding complements and for outputting a first output signal having a logic state representative of the results of a logic function performed on said first set of input signals and a second circuit branch including second input switching devices for receiving the complement of the at least two input signals and can include the at least two input signals and for outputting a non-inverted output signal. First and second input switching devices are configured so as to cause the latch to perform logic functions on the input signals and latch output states corresponding to the results logic functions on its non-inverted and inverted outputs in the same clock phase.

High-speed logic embodied differential dynamic CMOS true single phase

An electronic device is delineated comprising, in combination, a Phased Lock Loop (PLL) having a charge pump, and a mixed signal circuit coupled in parallel to the charge pump. The mixed signal circuit includes analog circuitry for adding charge to and removing charge from capacitors in a Low Pass Filer (LPF) of the PLL. The mixed signal circuit also includes digital circuitry for controlling the initiation and termination of both the charging and discharging operations carried on by the analog portion of the mixed signal circuit. Upon a significant change in system frequency, the mixed signal circuit first fully discharges and then rapidly charges the capacitors in the LPF in a manner which results in a significant reduction in PLL locking time.

Phase-locked loop having improved locking times and a method of

A power-on-reset (POR) circuit having a reduced sized charging capacitor is described which includes a voltage detection portion, a delay portion, and a POR signal generation portion. The voltage level detection portion functions to provide a level indicator signal after the power supply has reached a predetermined voltage level. The delay portion in response to the level indicator signal indicating that the power supply is greater than or equal to the predetermined voltage level charges a chargeable node to an inverter trip point voltage level in a predetermined delay time interval dependent on a capacitive element and a diode connected MOS device both connected to the chargeable node. The POR signal generation portion, in response to the voltage trip point level on the chargeable node, outputs a POR signal an extended time interval afterwards. The diode connected MOS device coupled to the chargeable node adds capacitance to the node and diminishes charging current as the node charges thereby allowing for the reduction in size of the capacitive element and a substantial reduction in size of the overall POR circuit layout size.

Power-on-reset circuit having reduced size charging capacitor

The present invention relates to a system and method for programming VROM links. The system has an address selection circuit connected to the VROM link for selecting an address in the VROM link in which to program. A polarity control circuit is also connected to the VROM link. The polarity control circuit allows one to control the directional flow of a current used in programming the VROM link.

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Scottsdale, AZ, United States of America

John C Ciccone