Irvine Sensors Corporation

Isc8 Inc.

John C Carson

Stewart A Clark

Volkan H Ozguz

Paul F Dahlgren

Ying Wen Hsu

Medhat Azzazy

Christ H Saunders

Robert Edward DeCaro

Michael K Miyake

Stuart N Shanken

Raphael R Some

Ronald J Indin

A neural logic unit network acting as an agent to achieve machine or device consciousness and intent is disclosed. More specifically, an agent of consciousness and intent (The Agent) is disclosed consisting of neuronal logic units upon which are mapped and connected to the individual outputs of the host system's entire sensorium and which neuronal logic units are activated by the simultaneous presentation of the results of the host system's recognition, tracking, analyses and characterization computations similar to those performed by biological unconscious brains. The embodiment of the assembly of neural logic units is referred to as Hyper Aware Logic.

Hyper aware logic apparatus and method to create an agent of consciousness and intent for devices and machines

A neural logic unit network acting as an agent to achieve machine or device consciousness and intent is disclosed. More specifically, an agent of consciousness and intent (The Agent) is disclosed consisting of neuronal logic units upon which are mapped and connected to the individual outputs of the host system's entire sensorium and which neuronal logic units are activated by the simultaneous presentation of the results of the host system's recognition, tracking, analyzes and characterization computations similar to those performed by biological unconscious brains. The embodiment of the assembly of neural logic units is referred to as Hyper Aware Logic.

Hyper aware logic to create an agent of consciousness and intent for devices and machines

An artificial synapse array and virtual neural space are disclosed. More specifically, a cognitive sensor system and method are disclosed comprising a massively parallel convolution processor capable of, for instance, situationally dependent identification of salient features in a scene of interest by emulating the cortical hierarchy found in the human retina and visual cortex.

Apparatus comprising artificial neuronal assembly

A device and method for the detection of one or more gases is disclosed. A MEMS structure comprising a micro gas cell array is provided comprising one or more micro gas cells having a predetermined gas therein. The micro gas cells define an optical path therethrough and may comprise a micro lens. Electromagnetic energy from a scene is collected and passed through one or more micro gas cells whereby electromagnetic energy emitted or reflected from a gas of interest in a scene is absorbed by a substantially identical gas contained within a micro gas cell. In this manner, the micro gas cell acts as a spectral filter. The electromagnetic outputs of the micro gas cells, which may comprise one or more spectrally inert micro gas cells, are received by one or more detector elements such as a photon detector array. The ratio of the outputs of the related detector elements are computed by processing electronics, resulting in the identification of the gas of interest.

Micro gas cell array device and method

A compact multi-stage switching network (), and a router () incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports () to selected ones of a second plurality of output ports () comprising: a first stack () of IC switching layers () that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (); a second stack () of IC switching layers () that are stacked in physical contact with one another, each IC switching layer () containing at least one switching element circuit (); and interconnecting circuitry () that connects the first stack () of IC layers to the second stack () of IC layers to form the compact multi-stage switching network. The stacks () are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits () and a suitable superconducting cooling housing (), as permitted by the compact nature of the multi-stage switching network (), in order to operate at high speed and low power.

High speed switching module comprised of stacked layers incorporating t-connect structures

A compact multi-stage switching network ( ), and a router ( ) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports ( ) to selected ones of a second plurality of output ports ( ) comprising: a first stack ( ) of IC switching layers ( ) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit ( ); a second stack ( ) of IC switching layers ( ) that are stacked in physical contact with one another, each IC switching layer ( ) containing at least one switching element circuit ( ); and interconnecting circuitry ( ) that connects the first stack ( ) of IC layers to the second stack ( ) of IC layers to form the compact multi-stage switching network. The stacks ( ) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits ( ) and a suitable superconducting cooling housing ( ), as permitted by the compact nature of the multi-stage switching network ( ), in order to operate at high speed and low power.

High speed multi-stage switching network formed from stacked switching layers

A neural processing module is disclosed which combines a weighted synapse array that performs &ldquo;primitive arithmetic&rdquo; (products and sums) in parallel with a weight change architecture and a data input architecture that collectively maximize the use of the weighted synapse array by providing it with signal permutations as frequently as possible. The neural processing module is used independently, or in combination with other modules in a planar or stacked arrangement.

Neural processing module with input architectures that make maximal use of a weighted synapse array

Stacked, multimodular circuit assemblies are provided which comprise stacked, resealable, modules containing electronic circuitry, each module having a plurality of electrically conductive, embedded through-vias between the upper and major surfaces thereof. The through-vias are contained within the module matrix outside of the circuit-containing cavity or 'tub' of the module and within the outer edges of the module body. Electronic circuitry contained in the module cavity is electrically connected to the through-vias by signal traces or vias passing out of the cavity and into contact with the through-vias, and adjacent modules are electrically interconnected by a resealable, multichannel connector array between adjacent modules having electrically conductive channels coupling opposing through-vias of the adjacent modules. The connector arrays can also serve to seal the assembly when the entire assemblage of modules is compressed and to connect the stacked modular assembly to exterior circuitry such as a printed circuit board or other device. Methods are also provided for assembling and electrically interconnecting electronic components within such stacked multimodular assemblies by attaching components of an electronic circuit to at least two stackable modules of the type described within the cavity thereof, interconnecting the circuit components with the described through-vias, and stacking and interconnecting the stackable modules with the described multichannel connector arrays interposed between each adjacent module pair.

Stackable modules and multimodular assemblies

An electronic module comprising a multiplicity of prestacked IC chips, such as memory chips, and an IC chip, referred to as an active substrate or active backplane, to which the stack of chips is directly secured. A multiplicity of aligned solder bumps may interconnect the stack and the substrate, providing electrical, mechanical and thermal interconnection. The active substrate is a layer containing substantial amounts of integrated circuitry, which interfaces, on one hand, with the integrated circuitry in the stacked chips, and, on the other hand, with the external computer bus system. Some of the high priority circuitry which may be included in the substrate is used for control, fault-tolerance, buffering, and data management.

Electronic module comprising a stack of IC chips each interacting with

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Module comprising IC memory stack dedicated to and structurally combined

This application discloses hardware suitable for use in a neural network system. It makes use of Z-technology modules, each containing densely packaged electronic circuitry. The modules provide access planes which are electrically connected to circuitry located on planar surfaces interfacing with such access planes. One such planar surface comprises a resistive feedback network. By combining two Z-technology modules, whose stacked chips are in planes perpendicular to one another, and using switching networks between the two modules, the system provides bidirectional accessibility of each individual electronic element in the neural network to most or all of the other individual electronic elements in the system.

Hardware for electronic neural network

A thermal imaging system is disclosed in which infrared radiation from the viewed scene is transmitted to a two-dimensional detector array carried on the focal plane of an optical/electronics module which has embedded in it amplifying, filtering and multiplexing circuitry utilizing MOSFET transistors. The module is located inside the cooling device. Cooling requirements depend on the alternatives (a) of using detectors responsive to wavelengths in the 3.0 to 5.0 micron range, which require less cooling, or (b) of using detectors responsive to wavelengths in the 8.0 to 12.0 micron range, which require liquid nitrogen cooling. The two-dimensional detector array may be combined with a limited scanning, called 'nutation', which causes each detector to view a plurality of pixels in the incoming infrared radiation.

Thermal imager incorporating electronics module having focal plane

A photodetector sensing system is disclosed which combines staring and scanning features. By providing both temporal and spatial filtering, many system benefits are obtained. Each pixel in the viewed scene has a 'dedicated' filter, which receives signals only from that pixel. By integrating time spaced signals from the same pixel, the filter maintains the staring effect of a two-dimensional detector array. A single detector may view a plurality of pixels, thereby improving resolution. A single pixel may be viewed by a plurality of detectors, thereby providing redundancy to correct for detector failures. The signal from each detector, after amplification, is first sent through a spatial, high frequency filter, and then is set to one of a plurality of parallel temporal, low frequency filters, which time share the detector. Synchronizing means are provided for ensuring that each temporal filter always receives its time spaced signals from the same source. Any suitable scanning mechanism may be used. The system may be used either to distinguish a moving target from a non-moving background, or to distinguish a non-moving target from a moving background.

Combined staring and scanning photodetector sensing system having both

A photo-detector array module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of photo-detectors on the focal plane end, and of thin film circuitry on the back plane end, each plane is etched to cut back the semiconductor material, then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Detector array module fabrication process

A high-density electronic package module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, each access plane is etched to cut back the semiconductor material then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Growing community of inventors

Corona Del Mar, CA, United States of America

John C Carson