Tektronix, Inc.

John C Calvin

Daniel G Knierim

Patrick A Smith

Kalev Sepp

Kan Tan

Marc A Gessford

Mark W Nightingale

Que Thuy Tran

David L Kelly

Mark L Guenther

Michael J Wadzita

John F Stoops

Shane A Hazzard

Gary K Richmond

Kelly F Cushing

Ramachandra Cv

John C Delacy

Marie Ottum

A dF/dT trigger system and method includes instantaneously triggering on a frequency deviation of a data signal, which can be associated with an SSC signal. After receiving a signal at an input terminal of a test and measurement instrument, the signal is low-pass filtered and transmitted to trigger circuitry. When a frequency deviation rate in the filtered signal exceeds or crosses one or more thresholds, a trigger event is produced. Also disclosed is a test and measurement instrument including an input terminal to receive the signal, input circuitry to receive and process the signal, and dF/dT trigger circuitry configured to receive the signal and produce a trigger event when a frequency deviation in the signal exceeds or crosses one or more thresholds.

DF/dT trigger system and method

An Arbitrary Waveform Generator has a controller programmed to generate a sequence of test waveforms using previously-defined waveform data files. The controller generates this series of test waveforms by direct synthesis to cause each waveform to contain a respective different predetermined amount of Rj, Sj and ISI jitter components. In this way, the Arbitrary Waveform Generator produces a sequence of waveforms incorporating varying amounts of ISI to sweep the ISI jitter components from an initial amount of ISI, for example, zero ISI, and continually increment the amount of ISI to a full unit interval of ISI in predetermined increments, for example, 0.1 UI steps.

Synthesis and generation of arbitrary waveforms with ISI components for jitter tolerance

An Arbitrary Waveform Generator (AWG) synthesizes and generates an SSC modulated signal by generating a modulating waveform with a frequency of an SSC modulation frequency, calculating the number of samples per data bit (SPUI) as a ratio of an upsampling frequency to a data rate of a data stream, calculating an amplification factor as the ratio of SSC deviation frequency to data rate of the data stream, generating the array of SSC Edges containing the edge variation with respect to single sample per bit, multiplying the amplification factor to the modulating waveform, generating an array of SSC Edges Upsampled, containing edge variations with respect to an Upsample factor per bit, and multiplying SSC Edges with SPUI; calculating the resultant bit duration SSC Bit Duration as the sum of SSC Edges Upsampled and SPU, and calculating the successive summation of SSC Bit Duration, to get SSC Bit Position.

Apparatus and method for synthesizing and generating an SSC modulated signal

A method of measuring transport delay and jitter with a realtime oscilloscope using cross-correlation acquires waveforms from two test points in a system under test. Clock recovery is run on both waveforms to obtain respective rates and offsets. A time offset between the two waveforms is computed. The jitter from the two test points is filtered and a mean-removed cross-correlation coefficient is computed from the filtered jitters. A fractional delay is computed using interpolation based on LMS error, and the respective computational components are summed to compute a transport delay between the two test points. The transport delay may be used to adjust clock edges from one waveform for comparison with data transition edges of the other waveform to measure jitter.

Transport delay and jitter measurements

An encoded serial data bit error analyzer captures the actual waveform of an encoded serial data stream associated with a bit error so that a user may readily validate the cause of the bit error. An encoded serial data stream decoder in the analyzer is modified to provide a signal for a trigger system when a characteristic of a bit error failure is detected. A power splitter produces a pair of incident encoded serial data streams from a programmable test signal, one of which is input to a device under test and the other is input to the analyzer. A re-transmitted encoded serial data stream from the device under test is input to another channel of the analyzer. The encoded serial data stream decoder provides an 'error detected' output when a condition occurs in the re-transmitted encoded serial data stream indicative of a bit error. The 'error detected' output is used as a trigger signal to capture the incident and re-transmitted encoded serial data waveforms surrounding the detected bit error.

Encoded serial data bit error detector

An advanced trigger circuit includes two trigger decoders, each triggering on one of respective pluralities of continuous-time trigger events. In one embodiment, a programmable timer begins timing in response to an output signal of the first trigger decoder and generates an end-of-time signal at the expiration of its time period. A reset circuit resets the first trigger decoder if the second selected continuous-time trigger event failed to occur before the end-of-time signal was generated. In another embodiment, a reset decoder generates a reset signal in response to an occurrence of a selected continuous-time trigger event. The reset circuit is responsive to the reset signal for resetting the first trigger decoder if the second selected continuous-time trigger event failed to occur before the reset signal was generated. In other embodiments, the advanced trigger circuit triggers on a serial lane skew violation or on a beacon width violation.

Oscilloscope having advanced triggering capability

A first method for rendering an eye diagram synchronized to a recovered clock and based on a single shot acquisition of a digital storage oscilloscope, acquires a waveform and measures the timing of its edges. It then estimates the symbol rate of the waveform and derives clock signals in accordance with the edge timing and the estimated symbol rate. The waveform data is then sliced into frames with respect to the derived clock signals, and the frames are partially overlapped and aligned to form an eye diagram. In a second embodiment of the invention, the frames are aligned, without being overlapped, to form an eye diagram.

Method for optimized rendering of eye diagrams synchronized to a recovered clock and based on a single shot acquisition

A deskew fixture has a multilayer circuit board from which pairs of mirrored signal launch contact extend from both sides of the circuit board. One pair of contacts is coupled to electrical ground and the other pair is connected via equal length, electromagnetically coupled strip lines to a signal source. Probe holders are mounted on the circuit boards to support measurement probes with the probing contacts of the measurement probes coupled to the signal launch contacts. Additional pairs of signal launch contacts may be provided with one pair receiving a positive signal from the signal source and another pair receiving a negative signal via equal length, electromagnetically coupled strip lines from the signal source for deskewing differential measurement probes.

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Portland, OR, United States of America

John C Calvin