International Business Machines Corporation

Globalfoundries Inc.

Jeol Usa, Inc.

John Bruley

Jeng-Bang Yau

Kam-Leung Lee

Jack Oon Chu

Paul Michael Solomon

Ahmet Serkan Ozcan

Alexander Reznicek

Ali Khakifirooz

Pouya Hashemi

Takashi Ando

Karthik Balakrishnan

Yun Yu Wang

Vijay Narayanan

Christian Lavoie

Eduard Albert Cartier

Markus Brink

Yun-Yu Wang

John Albrecht Ott

Martin O Sandberg

Vivekananda P Adiga

Anthony Gene Domenicucci

Benjamin B Wymore

Devendra K Sadana

Stephen W Bedell

Keith E Fogel

Cyril Cabral, Jr

Kenneth Parker Rodbell

Martin Michael Frank

Sandra Guy Malhotra

Dirk Pfeiffer

Peilin Song

Stephen Mark Rossnagel

David Lee Rath

John Rozen

Chao-Kun Hu

Hongwen Yan

Terence Lawrence Kane

Roy Arthur Carruthers

Eric Gerhard Liniger

Lynne Marie Gignac

John Gerard Gaudiello

Michael Abramovich Gribelyuk

Michael P Tenney

Jean-Oliver Plouchart

Tina Jane Wagner

Adam M Pyzyna

Marinus J P Hopstaken

Masahiro Kawasaki

Cihan Kurter

Horati S Wildman

Wong Kwong Hon

A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

Devices, systems, methods, and/or computer-implemented methods that can facilitate protection of a substrate in a qubit device using sacrificial material are provided. According to an embodiment, a device can comprise a superconducting lead provided on a pillar of a sacrificial material provided on a substrate. The device can further comprise a collapsed superconducting junction provided on the substrate and coupled to the superconducting lead.

Sacrificial material facilitating protection of a substrate in a qubit device

Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier. In various embodiments, the shadow evaporation process can further comprise depositing a first superconducting material on the substrate after the patterning the resist stack, oxidizing a surface of the first superconducting material to form the tunnel barrier, and depositing a second superconducting material over the protected portion of the tunnel barrier to form a Josephson junction. In various instances, the etching the exposed portion of the tunnel barrier can occur after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material.

Spurious junction prevention via in-situ ion milling

A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.

Grain size control of superconducting materials in thin films for Josephson junctions

A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.

Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or III-V channel of semiconductor device

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn) extension implant junction. The method includes forming a semiconductor fin on a substrate. A gate is formed over a channel region of the semiconductor fin. A Sn extension implant junction is formed on a surface of the semiconductor fin in the channel region.

Shallow, abrupt and highly activated tin extension implant junction

CMOS-compatible non-filamentary RRAM devices and techniques for formation thereof are provided. In one aspect, a method of forming a non-filamentary RRAM device includes: depositing a base oxide layer (e.g., hafnium oxide) on a bottom electrode; depositing a cap layer (e.g., amorphous silicon) on the base oxide layer; and depositing a top electrode on the cap layer, wherein the cap layer and the top electrode are deposited in-situ without any air exposure in between such that there is an absence of oxide at an interface between the cap layer and the top electrode. A low resistivity layer can optionally be deposited on the top electrode. An RRAM device and a computing device having a crossbar array of the present RRAM cells are also provided.

CMOS compatible non-filamentary resistive memory stack

Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.

High germanium content silicon germanium fins

An inline dark field holographic method for measuring strain in a semiconductor or other crystalline material using a transmission electron microscope having an electron gun for passing an electron beam through strained and unstrained specimens. A condenser mini-lens between the magnetic tilting coil and the specimens increases defection of the beam at an angle with prior to passing through the pair of specimens. The first objective lens forms a virtual image of each of the specimens and the second objective lens focuses the virtual images of each of the specimens at an intermediate image plane to form intermediate images of each of the specimens. The biprism creates the interference pattern between the specimens is formed at the image plane, which may then be viewed to determine the degree of strain of the strained specimen and provides a coma-free strain map with minimal optical distortion.

Method of producing an un-distorted dark field strain map at high spatial resolution through dark field electron holography

The present disclosure relates to a secure device having a physical unclonable function and methods of manufacturing such a secure device. The device includes a substrate and at least one high-k/metal gate device formed on the substrate. The at least one high-k/metal gate device represents the physical unclonable function. In some cases, the at least one high-k/metal gate device may be subjected a variability enhancement. In some cases, the secure device may include a measurement circuit for measuring a property of the at least one high-k/metal gate device.

Reliable physical unclonable function for device authentication

Growing community of inventors

Poughkeepsie, NY, United States of America

John Bruley