Texas Instruments Corporation

John Britton Robbins

Scott Robert Summerfelt

Byron Lovell Williams

Lawrence D Dyer

Stephen Arion Meisner

Ricky L Boston

Jeffrey Alan West

Asad Mahmood Haider

Eugene C Davis

Jerry B Medders

Mohendra S Bawa

Jerry D Smith

Franklin L Allen

Vikki S Simpson

Michael Cunningham

A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.

Method and device for patterning thick layers

Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.

Process for forming PZT or PLZT thinfilms with low defectivity

The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor.

High-resistance thin-film resistor and method of forming the resistor

An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

Alignment mark for opaque layer

The protection to the backside of the semiconductor wafer is accomplished by applying a layer of silicon oxide or silicon nitride or other deposited material to the back surface of a semiconductor wafer to protect against particles, scratches, and etching by mild caustic solutions. The layer remains in place during all three processes, edge pre-polish, mirror edge polish, and wafer polish.

Method of surface protection of a semiconductor wafer during polishing

A method of backside damaging a silicon semiconductor wafer by abrading the wafer in an abrasive powder is disclosed. The wafer is rotated or translated in the powder while the powder is being vibrated. A fixture holds one or more semiconductor wafers during the processing and allows the wafer to be rotated during processing if desired.

Method and apparatus for back side damage of silicon wafers

Method for backside damage of silicon wafers

Trace quantities of elemental iodine are added to deionized water used in the manufacture of semiconductor materials and devices in order to sterilize the water and the delivery system of microscopic life forms, and to leave the iodine in the flow all the way through processing except for those process steps where iodine may be detrimental to the process step.

Growing community of inventors

McKinney, TX, United States of America

John Britton Robbins