Rambus Inc.

Other

Xerox Corporation

John Bradly Dillon

Frederick Abbott Ware

Richard Maurice Barth

Matthew Murdy Griffin

Craig Edward Hampel

Billy Wayne Garrett, Jr

Donald C Stark

Donald Victor Perino

Michael P Farmwald

Wayne S Richardson

Mark A Horowitz

William Franklin Stonecypher

Michael Tak-Kei Ching

Andy Peng-Pui Chan

Richard DeWitt Crisp

John Girdner Atwood, Jr

Kevin S Donnelly

Mark G Johnson

James A Gasbarro

Chanh Vi Tran

John G Atwood

Ely K Tsern

Alfredo Moncayo

William C Lynch

Geoffrey O Thompson

Jonathan J Gibbons

Clemenz L Portmann

Donald R Woods

Srinivas Nimmagadda

Perry A Caro

Michael L Tallan

Charles R Fay

Joseph H Binkley

Abdo G Kadifa

Clayton W Mock

Everett T Neely

Gaya Vukkadala

Jeffery W Lee

John D Wick

By Nancy David Dillon

Hilary N Hooks

Paul G Davis

Pradeep Batra

Nancy David Dillon, Legal Representative

Karnamadakala Krishnamohan

Donald Charles Stark

Frederick Abbot Ware

In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Transceiver with latency alignment circuitry

Embodiments of the present invention provide a cover for a Packaged Terminal Air Conditioning (PTAC) unit. Embodiments of the cover include a gasket on an interior portion of the cover sealing against a portion of the PTAC unit to prevent air recirculation. Other embodiments of the cover include a screen configured to capture large debris. Other embodiments of the cover include solid wood panels with stain and lacquer on both sides of the panels.

Cover for a wall-mounted packaged terminal air conditioning (PTAC) unit

The socket releasably couples a packaged integrated circuit to a circuit board. The socket includes a clamp, a latch, and an array interconnect. The clamp is configured to be pivotally coupled to a circuit board. The latch is configured to be coupled to the circuit board and configured to releasably hold the clamp in a predetermined position. The array interconnect configured to be coupled to the printed circuit board. In use the latch releasably holds the hinged clamp in the predetermined position to clamp both a packaged integrated circuit between the clamp and the array interconnect, and the array interconnect between the packaged integrated circuit and the circuit board.

Chip socket assembly and chip file assembly for semiconductor chips

Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is provided to the memory device during an odd phase of the clock signal.

Method of controlling a memory device having a memory core

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

Memory integrated circuit device which samples data upon detection of a strobe signal

A system and method for performing data transfers within a computer system is provided The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

Protocol for communication with dynamic memory

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Apparatus and method for pipelined memory operations

A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.

A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode. The memory device is operable in a normal read operation upon exiting the calibration mode. During the normal read operation, the first output driver is operable to output data onto the first signal line in accordance with the calibrated voltage swing level.

Memory system including a memory device having a controlled output driver characteristic

A synchronization circuit for gradually shifting the phase domain of a control signal to permit synchronization of a signal with a clock signal in a different phase domain in a system with a single frequency, but arbitrary phase relationship. The present invention allows a control signal in the phase domain of an internal clock to be synchronized with an external clock, when the phase domain of the external clock differs substantially from that of the internal clock. In synchronizing the control signal to the external clock, the present invention avoids the generation of runt pulses while providing a control signal synchronized to the external clock in the least amount of time feasible (i.e., with the lowest latency time). Because the present invention has no failure modes due to timing relationships, MTBF is infinite for failures caused by such relationships and therefore need not be a concern. This also implies that no risk is posed to the proper operation of the circuits driven thereby.

Apparatus and method for synchronizing a control signal

A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

Semiconductor controller device having a controlled output driver characteristic

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Palo Alto, CA, United States of America

John Bradly Dillon