Intel Corporation

John Beaston

Robert L Farrell

Raymond Scott Tetrick

Steven D Kassel

Edwin L Jacks, Jr

Alireza Sarabi

Sudarshan Balachandran

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as 'agents') to permit the exchange of data and messages at high speed using a minimum of 'handshake' events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.

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Hillsboro, OR, United States of America

John Beaston