Siemens Aktiengesellschaft

Gte Communication Systems Corporation

Gte Communications Products Corporation

Siemens Communication Systems, Inc.

John B McNesby

Angel L Rodriguez

Amritpal S Kalla

David C Crohn

Erik K Walker

Joseph F Krys

A system for determining the presence or absence of data on one or more data lines including a flip-flop for each data line with the output of each flip-flop connected to a NAND gate. The NAND gate is connected through an OR gate to two output flip-flops in series. The logic of the system is such that the output of the second of the two output flip-flops provides a signal level which is high or low depending on whether data is present on all of the data lines or one or more lines has no data.

System for determining loss of activity on a plurality of data lines

A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. To provide a relatively large window of time for looking at the data, parallel data is obtained by providing a parallel-to-parallel register at the output of a serial-to-parallel register. The parallel data is added to the held polynomial by a series of exclusive OR gates.

Parallel scrambler used in SONET data transmission

A data scrambler circuit which adds the SONET polynomial 1+X.sup.6 +X.sup.7 to data in a parallel format to thereby reduce circuitry clock rates to one-eighth the line rate, which reduces power consumption and simplifies timing constraints. A circuit embodiment includes a first series of flip-flops connected to generate the polynomial and a second series of flip-flops for holding the generated polynomial. The parallel data is added to the held polynomial by a series of exclusive OR gates.

Parallel scrambler used in sonet data transmission

A frame error detection system for SONET which operates in both the OC-3 and OC-12 modes. The frame detection circuit operates by examining the incoming data bit stream, which is in parallel form, detecting A1 and A2 bytes and if, in the OC-3 mode, three consecutive A1 bytes are received, followed by three A2 bytes, then framing is correct. If one of these bytes is missing, then there is an error in framing. The bytes, as they are received and processed by the system, are stored in a series of flip-flops and the output logic signal therefrom is indicative of the framing condition as to whether it is correct or errored.

Frame error detection system

A frame detection circuit for SONET which operates in both the OC-3 and OC-12 modes. The frame detection circuit operates by examining the incoming data bit stream, detecting A1 and A2 bytes, and counting three consecutive A1 bytes immediately followed by three consecutive A2 bytes. Since the counters recycle upon reaching a three count, the circuit works for both the OC-3 and OC-12 modes.

Frame detection system

In a data transmission system, apparatus for converting a subrate binary data stream into a binary signal at the line transmission rate comprises means for periodically accepting a date byte from the subrate data stream and; means for expanding the data byte by one additional bit by adding a control bit in the first bit position of the accepting means. The apparatus additionally comprises means for recirculating the expanded data byte through the accepting means a predetermined number of times and means for serially reading out bits of the expanded data byte at the line transmission rate.

Data transmission by subrate grouping

A data rate converter for use in telecommunications inserts supervisory bits into a data stream to increase the data rate, in one application, from 56 kbps to a standard 64 kbps. A standard 64 kbps PCM telephone channel uses 8-bit words for transmission, whereas 56 kbps occupies only 7 bits of an 8 bit word in such a telephone channel. Supervisory bits are inserted at the exact time when the data channel clock signal and the transmission line clock signal are in phase alignment.

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Mesa, AZ, United States of America

John B McNesby