Intel Corporation

Micron Technology Incorporated

John B Matovu

Sri Sai Sivakumar Vegunta

Gowrisankar Damarla

Gordon A Haller

Lifang Xu

David A Daycock

Matthew J King

Kunal Shrotri

Suresh Ramarajan

Matthew Park

Jivaan Kishore Jhothiraman

Prakash Rau Mokhna Rau

Rithu K Bhonsle

Jun Zhao

Rutuparna Narulkar

David S Meyaard

Kevin R Gast

Shashank Saraf

Gowrisankar Damaria

A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

Stair step structures including insulative materials, and related devices

A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Solid state memory component

Semiconductor devices including a stair step structure, and related methods

Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

Methods of forming semiconductor structures having stair step structures

A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.

Growing community of inventors

Boise, ID, United States of America

John B Matovu