U.S. Philips Corporation

Koninklijke Philips Corporation N.V.

Other

John B Hughes

Kenneth W Moulding

Desmond R Armstrong

William Redman-White

Mark Bracey

Ian C MacBeth

Cover means () for a wineglass or like container () are made from a flat sheet (), and comprise means () adapted to be bent from the sheet () and used to inhibit the cover means () from slipping off the container, which inhibiting means () comprise an inhibiting element (), e.g. a tab (), adapted to be bent from the sheet at one or more bends () inwards of the periphery () of the cover means (), whereby the whole of said element () is located inwards of and spaced from the periphery () or at least one said bend () extends inwards from said periphery (). Two, three or more of said elements () may be adapted to be inside and/or outside the rim () of the container (). Such an element () may point radially or circumferentially, and may be cut from the sheet () (or have a lineof weakening for ready separation from the sheet) apart from at said bend (). Said elements () may be spaced apart around the cover means () and/or at different distances from a center to suit the diameters of respective said containers (). A non-tab form said element () may have a cross-section of V-shape in a circumferential direction. The cover means () may be formed into a conical shape, e.g. by interlocking means (), e.g. comprising hook means (), or be held in conical shape by bending alone; and/or may be adapted to be such that the action of using a finger to apply pressure downwards at one portion of the outer edge of the cover () will lever the cover () up at the opposite side of the container ().

Covers for wineglasses or like containers

A transconductor circuit, such as a gyrator filter, comprises an arrangement of balanced class AB transconductors, capacitors and floating MOS resistors formed by MOS transistors operating in their triode region. Tuning of the filter is effected by varying a common supply rail voltage. The circuit includes a means for producing a voltage offset from the common mode voltage of the class AB transconductors. The offset voltage is supplied to a parallel arrangement of a class AB transconductor having a transconductance and the source-drain path of a MOS transistor emulating a MOS resistor. The current output of the parallel arrangement is integrated and supplied as a control voltage to the gate electrode of the MOS transistor. By loop action the control voltage is adjusted and supplied to the floating MOS resistors.

Transconductor circuits

A comparator is provided that compares one or more input signals in a regenerative circuit. One or more switched isolate the signal inputs after regeneration has started but before regeneration has reached such an extent that large voltage swings in the regeneration circuit are transmitted back to the signal source and corrupt the signal source or neighboring circuits. Furthermore, as controlled by a control circuit, the instant of isolating the signal source can be dependent on the degree of regeneration such as being dependent on a predetermined degree of regeneration. The comparator may be incorporated in an electronic device such as an analog-to-digital converter or a wireless receiver or transceiver.

Clocked comparator circuit

A complex switched-current bilinear integrator () is formed as a pair of cross coupled real bilinear integrators and has inputs () and outputs () for differential pairs of in-phase () and quadrature-phase (Q) signals and an arrangement of sample-and-hold circuits () and coupled scaling circuits (). Dynamic element matching is used to reduce the effect of mismatch between scaling circuits by interchanging scaling circuits in different signal paths. In order to prevent cross-talk of signals between different signal paths, the change of a scaling circuit coupled to a sample-and-hold circuit is constrained to occur only at the beginning of a sampling operation by that sample-and-hold circuit.

Switched-current integrator

An current mode analogue-to-digital converter uses a conversion stage which operates using a two-phase clock and which requires the input signal to be present during only one of the phases. A sample-and-hold circuit () samples the input signal during the first clock phase and during the second clock phase a quantised bit value is generated from a mirror of the held input current by a kickback-free comparator circuit (). Also during the second clock phase a residue is generated using the quantised value and a non-mirrored version of the held input current. Optionally, two comparator circuits () may be used to provide two-level quantisation, enabling errors introduced by the current mirror to be corrected by a Redundant Signed Digit algorithm. Two pipelines of conversion stages (S', S&#x2033;) can be multiplexed to double the conversion rate.

Switched-current analogue-to-digital converter

A balanced transconductor having a pair of voltage inputs and a pair of current outputs comprises a pair of single-ended transconductors, one in each signal path and a cancellation network. The cancellation network cancels at the inputs to the single-ended transconductors a common mode voltage appearing at the voltage inputs so that no common mode output current results. The cancellation network may comprise four half-size single-ended transconductors drawing half the supply current of full-size single-ended transconductors.

Balanced transconductor and electronic device

An integrated circuit ( ) comprising an analogue circuit ( ) and optionally a digital circuit ( ) couples substrate noise present on the integrated circuit ground rail ( ) onto a supply rail ( ) of the analogue circuit. The voltage difference between the supply rail and ground is therefore substantially independent of the noise, thereby reducing or eliminating the impact of the noise on signals in the analogue circuit.

Integrated circuit

In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is formed as two or more sub-transistors, the channel length of one sub-transistor being unequal to that of the other(s).

MOS transistor having first and second channel segments with different widths and lengths

A current mode pipelined analogue to digital converter (ADC) has a plurality of serially connected conversion stages. Each conversion stage has an input (,) for receiving a sampled and held current which is connected via a switch (S,) to a first current memory (M,) and via a switch (S,) to a second current memory (M,). The output of the second current memory (M,) is fed via a switch (S,) to one input of a summing junction (,). The output of the first current memory (M,) is fed via a switch (S,) to the input of a comparator (L,) whose output is clocked into a latch (L,) whose Q output is connected to an output (,) as the digital result of the conversion. The Q output of the latch (L,) is also connected to a digital to analogue converter (,) whose analogue output is fed to a second input of the summing junction,via a switch (S,) to form the analogue residue signal for application via output (,) to the next conversion stage in the pipeline. The stage has the advantage that the analogue signal is fed from stage to stage using only one current memory (M,) thus reducing transmission loss and that corruption of the analogue signal by comparator &ldquo;kick back&rdquo; is avoided by using a further current memory (M,) in parallel with the signal path current memory (M,).

Analogue to digital converter

A current comparator comprises first (1) and second (2) inputs for receiving input currents to be compared. During a first phase (1a) of a clock period the input currents are sensed and stored on first (N1,S7) and second (N2,S8) current memory circuits. On a second phase (1b) of the clock period a switching arrangement (S1 to S4) inverts the input currents and applies them together with the currents stored in the first (N1,S7) and second (N2,S8) current memory circuits to a regenerative latch circuit (P1,P2,S9,S10). During a third phase (2a) of the clock period the comparator produces the comparison result at an output (3). During a fourth phase switches (S5,S6,S9,S10,S11) are operated to reset the comparator to its initial state.

Current comparator

A switched current memory circuit has an input to which an input current (i) is applied and which is connected via a switch (S1) to the drain electrode of a memory transistor (M). A second switch (S3) is connected between the memory circuit input and the source electrode of a grounded gate transistor (G) whose drain electrode is connected to the gate electrode of the memory transistor (M). The drain electrode of the memory transistor (M) is connected via switch (S2) to an output at which an output current (i.sub.o) is produced. The second switch (S3) provides zero-voltage switching which reduces the effects of charge injection on the current stored.

Switched-current memory

A current memory cell comprises a fine MOS memory transistor (T1) and a coarse MOS memory transistor (T2) connected in series between two power supply rails. Such current memory cells are preferably designed so that the sum of the voltage drops across the coarse and fine memory transistors when diode connected is equal to the supply voltage. In order to achieve this while leaving flexibility in choosing the transistor saturation voltages an auxiliary power rail (V.sub.dda) is generated using as a reference the voltage drops across two diode connected transistors (T6, T7) which conduct a current equal to the bias current in the current memory cell (3).

Current memory and circuit arrangement comprising current memories

A current memory for sampled analogue currents comprises a first, coarse, current memory cell and a second, fine, current memory cell. The first current memory cell senses the input current during a first portion of the first period of the clock cycle, while the second current memory cell senses the input current plus the current produced by the first current memory cell during a second portion of the first period of the clock cycle. The combined outputs of the first and second current memory cells is available during a second period of the clock cycle. The first current memory further comprises a voltage amplifier which increases the effective g.sub.m of a memory transistor in the first memory cell and holds the potential at the junction of the drain electrodes of the memory transistors in each of the memory cells close to a virtual earth.

Current memory for sampling analog currents

Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories where the second current memory has a plurality of scaled outputs which feed switching arrangements. Resistors are provided in the current memories, the resistance of the resistors being equal to the 'on' resistance of the switching arrangement multiplied by any multiplying factor applied to this output to which the switching arrangement is coupled.

Switched current circuits

A current memory comprises an input which is connected via a switch which is closed on a phase .phi.1 of a clock signal to inputs of a coarse memory cell (M1) and a fine memory cell(M2). The coarse memory cell samples the input current on phase .phi.1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory on phase .phi.1b of the clock. A second switch which is closed on phase .phi.2 of the clock passes the combined outputs of the coarse and fine memories to an output. Two further switches are provided which are closed for a short time (sh1) at the start of phase .phi.1b. The two further switches discharge the stray capacitance (C.sub.n) at the node (2) to the voltage reference source via a terminal.

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Hove, United Kingdom

John B Hughes