Intel Corporation

Other

Tahoe Research, Ltd.

John B Halbert

Kuljit Singh Bains

Randy M Bonella

Chung Lam

Michael W Williams

James M Dodd

Zvika Greenfield

Robert M Ellis

Chris B Freeman

Christopher P Mozak

Theodore Zale Schoenborn

Jim M Dodd

Pete D Vogt

Christopher E Cox

David Zimmerman

Animesh Mishra

Andre Schaefer

Sandeep K Jain

Kjersten E Criss

Bill Nale

Herbert H Hum

Kenneth D Shoemaker

Bruce Querbach

Nadav Bonen

Warren Morrow

Debaleena Das

Brian P Johnson

Jay C Wells

David Wyatt

Rajat Agarwal

Randy B Osborne

Jun Shi

Dennis W Brzezinski

Tomer Levy

Bruce A Christenson

Uksong Kang

Melik Isbara

Shay Fux

Jin Kim

James A McCall

Aaron K Martin

Zuoguo Wu

Wei Wu

Andrew W Martwick

Thomas J Holman

Narendra S Khandekar

Suneeta Sah

Todd A Hinck

Hussein Alameer

Greg Lemos

A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Stacked memory with interface providing offset interconnects

A method performed by a memory is described. The method includes sensing first bits from a first activated column associated with a first sub-word line structure simultaneously with the sensing of second bits from a second activated column associated with a second sub-word line structure. The method also includes providing the first bits at a same first bit location within different read words of a burst read sequence and providing the second bits at a same second bit location within the different read words of the burst read sequence.

Memory with reduced exposure to manufacturing related data corruption errors

A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device can provide the error result to an associated host of the system to expose only a number of errors accumulated without exposing internal errors from prior to incorporation into a system. The memory device can be made capable to generate internal addresses to execute commands received from the memory controller. The memory device can be made capable to reset the counter after a first pass through the memory area in which errors are counted.

On-die ECC with error counter and internal address generation

An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Memory device error check and scrub mode and error transparency

A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.

Targeted aliasing single error correction (SEC) code

Embodiments are generally directed to performance of additional refresh operations during self-refresh mode. An embodiment of a memory device includes one or more memory banks, a mode register set, the mode register set including a first set of mode register bits, and a control logic to provide control operations for the memory device, the operations including refresh operations for the one or more memory banks in a refresh credit mode. The control logic is to perform one or more extra refresh cycles in response to receipt of a self-refresh command, the self-refresh command to provide current refresh status information, and is to store information in the first set of mode register bits regarding a modified refresh status after the performance of the one or more extra refresh cycles.

Performance of additional refresh operations during self-refresh mode

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.

Flexible command addressing for memory

A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

Stacked memory chip device with enhanced data protection capability

Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging of voltage levels representing stored data when read/write operations are idle. At least one register source provides a first voltage level and a second voltage level that is less than the first voltage level. With such a configuration, during the active mode, the memory device operates at the first voltage level as provided by the at least one register source, and during the self-refresh mode, the memory device operates at the second voltage level as provided by the at least one register source.

Reduction of power consumption in memory devices during refresh modes

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as 'hammered' or a 'row hammer event'), physically adjacent row (a &#x201c;victim&#x201d; row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Row hammer refresh command

Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises multiple memory banks. The memory controller further sends a signal specifying that the commands include back-to-back write commands each to access the same memory bank. In response to the signal, the memory device buffers first data of a first write command, wherein the first data is buffered at least until the memory device receives second data of a second write command. Error correction information is calculated for a combination of the first data and second data, and the combination is written to the memory bank. In another embodiment, buffering of the first data and combining of the first data with the second data is performed, based on the signal from the memory controller, in lieu of read-modify-write processing of the first data.

Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory

Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Precharging and refreshing banks in memory device with bank group architecture

Embodiments are generally directed to validation of memory on-die error correction code. An embodiment of a memory device includes one or more memory arrays for the storage of data; control logic to control operation of the memory device; and ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays. In a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.

Validation of memory on-die error correction code

Growing community of inventors

Beaverton, OR, United States of America

John B Halbert