International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Other

Marvell International Limited

Infineon Technologies North America Corp.

Globalfoundaries Inc.

John Atkinson Fifield

William R Tonti

Claude Louis Bertin

Wagdi William Abadeer

Russell J Houghton

Eric D Hunt-Schroeder

Darren Lane Anand

Harold Pilo

Nicholas Martin Van Heel

Mark David Jacunski

Howard L Kalter

Christopher P Miller

Louis L Hsu

Wayne Frederick Ellis

Albert Manhee Chu

Dale E Pontius

Anthony Richard Bonaccio

Kerry Bernstein

John Edward Barth, Jr

Karl Robert Erickson

Phil Christopher Paone

Norman Jay Rohrer

George Maria Braceras

Chin-Long Chen

Erik L Hedberg

Paul David Kartschoke

Lawrence G Heller

Robert J Gauthier, Jr

Philip George Emma

Chandrasekharan Kothandaraman

Michael Richard Ouellette

Wilbur David Pricer

Douglas Craig Bossen

William A Klaasen

Daniel W Storaska

Steven William Tomashot

Jack Allan Mandelman

Rajiv V Joshi

JunJun Li

Wayne John Howell

Jeffrey Scott Brown

Thomas George Ference

Thomas M Maffitt

Howard Hao Chen

Wing Kin Luk

Jeffrey H Dreibelbis

Richard Steven Kontra

Timothy Dooling Sullivan

Kevin William Gorman

Stephen Dale Wyatt

Jeremy K Stephens

Jeffrey Scott Zimmerman

Daryl Michael Seitzer

Ciaran J Brennan

David G Chapman

Tak H Ning

Mark Charles Hakey

Terence B Hook

Wendell P Noble

Toshiaki Kirihata

Kenneth Parker Rodbell

Frank David Ferraiolo

Igor Arsovski

Robert H Dennard

Stephen Victor Kosonocky

William Vincent Huott

William Paul Hovis

Randy William Mann

Li-Kong Wang

Tom C Lee

Kiran V Chatty

Jason D Hibbeler

Louis C Hsu

James Spiros Nakos

Michael Anthony Sorna

John E Gersbach

Steven Frederick Oakland

Peter Anthony Sandon

David E Lackey

Todd Morgan Rasmus

Lloyd Andre Walls

Barry Joe Wolford

Bradford Lawrence Hunter

Ronald Dennis Rose

Scott C Lewis

Tin-Chee Lo

John Robert Goss

Kenneth E Beilstein, Jr

Robert E Busch

Robert Maurice Houle

Wolfgang Hokenmaier

Kevin A Batson

Douglas Wayne Kemerer

Larry Wissel

Cathryn Jeanne Christiansen

Chandrasekara Kothandaraman

Pamela Sue Gillis

Chorng-Lii Hwang

Duane E Galbi

Jeffery Howard Oppold

Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.

On-chip reliability monitor and method

A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.

Charge pump circuit with internal pre-charge configuration

The present disclosure relates to a structure including a voltage selection circuit which includes a first device and a second device, the voltage selection circuit is configured to output a higher voltage of a first supply voltage and a second supply voltage through one of the first device and the second device, and a voltage difference between the first supply voltage and the second supply voltage is less than a threshold voltage.

Selection circuit

The present disclosure relates to a structure which includes a voltage level shifter circuit which includes a first current mirror leg circuit and a second current mirror leg circuit, the first current mirror leg circuit receives an input signal on a low voltage power supply and level shifts the input signal to a high voltage power supply which is at a greater voltage than the low voltage power supply, and the high voltage power supply is output from the second current mirror leg circuit.

Ultra-low voltage level shifter

A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

Voltage boost circuit

Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.

Charge pump circuit with built-in-retry

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

High speed level translator

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

Latching current sensing amplifier for memory array

An array of memory cells in rows and columns with each column having a corresponding reference cell and a corresponding comparator. Each memory cell in a given row and given column is connected to a memory wordline for the row and to a memory bitline for the column. Each reference cell is connected to a reference wordline for the reference cells and to a reference bitline. Each comparator for a column has a current mirror with a reference section connected to the reference bitline for the reference cell for the column and a memory section connected to the memory bitline for the memory cells in the column. Each reference section has a current mirror node and all current mirror nodes in the array are connected to reduce mismatch and improve sensing accuracy. Voltages applied to the memory and reference wordlines are varied to provide accurate single-ended sensing, margin testing, etc.

Memory array including distributed reference cells for current sensing

The present disclosure relates to a structure which includes a twin-cell memory which includes a first device and a second device and which is configured to store data which corresponds to a threshold voltage difference between the first device controlled by a first wordline and the second device controlled by a second wordline.

Margin test for multiple-time programmable memory (MTPM) with split wordlines

Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by &#xbd; DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by &#xbd; DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

On-chip calibration circuit and method with half-step resolution

The present disclosure relates to a structure which includes a current-mirror control node which is configured to adjust a current margin and provide the adjusted current margin to at least one one-time programmable memory (OTPM) cell.

Margin test for one-time programmable memory (OTPM) array with common mode current source

An electrostatic discharge protection circuit includes a power clamp device, a timing circuit including a first resistor, a first capacitor that is connected with the first resistor at a first node, and a second capacitor that is connected to a second node, a logic gate including a first input connected with the first node, a second input connected with the second node, and an output connected with the power clamp device, and a decoder device connected with a first address pin and a second address pin. The first address pin and the second address pin are used to detect the power clamp device switching on at time of power on and draining current.

Electrostatic discharge power clamp with fail-safe design

Growing community of inventors

Underhill, VT, United States of America

John Atkinson Fifield