Agere Systems Inc.

Lucent Technologies Inc.

John Anthony Pantone

Seung Hyuk Kang

Shahriar Moinian

John Michael Sharpe

Matthew Moucheron

Randall K Wolf

David A Kenney

Blane A Musser

Carl A Benevit

Kausar Banoo

Shane S Dias

Techniques are presented for reliability analysis of integrated circuits. A circuit data file including a connectivity network with appended parasitic information is obtained. Circuit performance is simulated, based on the data file, to obtain simulated currents for metallic conductive paths of the circuit. Contextual representations of the paths are determined, and reliability analysis is performed on the contextual representations. The analysis can relate, for example, to electromigration, joule-heating, and/or fusing. The results of the analysis can be provided, for example, in the form of a report including recommended changes, such as width increases, to wires for which it is determined that reliability issues exist.

Reliability analysis of integrated circuits

A process for evaluating and correcting virtual integrated circuit designs includes a method and apparatus for determining a ratio of an amount of material, i.e. polysilicon or metal, in any given layer to an area of the layer. The ratio is then compared to a predetermined target ratio, which is based on a ratio of the total amount of the material to the entire area of the I-C design. The process then automatically inserts or deletes an amount of material from the layer as needed, using any of four methods. These methods include deletion, scaling, deletion and scaling or striping. The ratio for an erroneous layer is rechecked after the first correction is performed and the entire process is repeated using a Newton-Raphson or a Least Absolute Deviation Regression method until the ratio falls within the predetermined tolerances. If the layer has been filled, the layer is further checked for short circuits, fill isolation violations, antenna violations and the like which may have resulted from the material fill. The evaluation and correction process proceeds for each layer of the virtual integrated circuit design until the entire design has been evaluated and corrected.

Method and apparatus for evaluating and correcting errors in integrated circuit chip designs

A user interface for a graphical application tool is disclosed. A graphical application tool is a software program, such as a computer-aided design (CAD) tool, a spreadsheet package, or a graphics drawing package, that graphically provides a user with a set of commands, tools and icons, which a user can graphically manipulate to generate, modify or analyze a work product in a work space area. The graphical application tool includes a graphical user interface (GUI) to provide users with a repositionable menu of available commands, tools and icons. The menu provides access to the commands, tools and device offerings without interfering with the user's work space area. In the illustrative computer-aided design (CAD) tool embodiment, the menu preferably provides a user with access to core and custom commands and circuit component offerings. Core commands presented in a core command section of the menu are preferably context-determined so that commands appropriate to the current operating mode of the graphical application tool are presented. Circuit component offerings presented in the device offering section of the menu are preferably technology-determined so that device offerings appropriate to the specified technology are presented. In other words, when the graphical application tool is initiated, the user is preferably queried for the type of technology the user will be designing with.

User interface for graphical application tool

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Birdsboro, PA, United States of America

John Anthony Pantone