International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Other

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries U.S. Inc.

Intermolecular, Inc.

Advanced Technology Materials, Inc.

Infineon Technologies North America Corp.

John Anthony Fitzsimmons

Mukta G Farooq

Anthony K Stamper

Jeffrey P Gambino

Timothy Joseph Dalton

Vincent James McGahay

Lee Matthew Nicholson

Edward Crandal Cooney, Iii

Daniel C Edelstein

Stephen McConnell Gates

Sampath Purushothaman

David Lee Rath

Darryl D Restaino

Tien-Jen Cheng

Andrew Herbert Simon

Michael Wayne Lane

Thomas M Shaw

Troy Lawrence Graves-Abe

Sujatha Sankaran

Matthew Earl Colburn

Elbert Emin Huang

Satyanarayana Venkata Nitta

Erdem Kaltalioglu

Ping-Chuan Wang

Ronald G Filippi

Terry Allen Spooner

Michael Beck

Jia Lee

Kangguo Cheng

Theodorus E Standaert

Shom Ponoth

Ravikumar Ramachandran

Laertis Economikos

Stephen Edward Greco

Spyridon Skordas

Mahmoud M Khojasteh

Russell Herbert Arndt

Jennifer V Muncy

John Ulrich Knickerbocker

Yun Yu Wang

Soon-Cheon Seo

Mark David Jaffe

Louis Lu-Chen Hsu

Tze-Chiang Chen

Muthumanickam Sankarapandian

Jeffrey Curtis Hedrick

Stephen Ellinwood Luce

Paul Charles Jamison

Thomas L McDevitt

Shyng-Tsong Chen

Michael Jay Shapiro

Shahab Siddiqui

Randy Lee Wolf

Terence Lawrence Kane

Roy Arthur Carruthers

Lewis Sigmund Goldmann

William E Bernier

Stephan Alan Cohen

Christy Sensenich Tyberg

Matthew S Angyal

Lijuan Zhang

Habib Hichri

Paul J Tsang

Brett H Engel

Horatio Seymour Wildman

Wuping Liu

Glenn A Biery

Geraldine C Schwartz

Marie S Cole

David E Eichstadt

Ranee Wai-Ling Kwong

Louis L Hsu

Ali Afzali-Ardakani

Ruqiang Bao

Oscar Van Der Straten

Sanjay C Mehta

Unoh Kwon

Richard Anthony Conti

Emanuel Israel Cooper

Naftali Eliahu Lustig

Wei Lin

Nicholas C M Fuller

Stephan Grunow

Kang-Wook Lee

William J Cote

Thomas J Fleischman

Nancy Anne Greco

Kevin R Winstel

Eric Gerhard Liniger

Lynne Marie Gignac

Erick G Walton

Stanley Joseph Whitehair

Henry Atkinson Nye, Iii

Karl E Boggs

George Gabriel Totir

Daewon Yang

Donna Rizzone Cote

Ernest N Levine

Kenneth M Davis

Chester T Dziobkowski

An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

SOI wafers with buried dielectric layers to prevent CU diffusion

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a semiconductor structure having a first metal layer and a plurality of dielectric layers on top of the first metal layer; creating one or more openings through the plurality of dielectric layers to expose the first metal layer underneath the plurality of dielectric layers; causing the one or more openings to expand downward into the first metal layer and expand horizontally into areas underneath the plurality of dielectric layers; applying a layer of lining material in lining sidewalls of the one or more openings inside the plurality of dielectric layers; and filling the expanded one or more openings with a conductive material.

Self aligned contact structure

Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

Device layer transfer with a preserved handle wafer section

One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include providing a substrate having a front side and a back side, the substrate including a deep trench (DT) capacitor within the substrate extending toward the back side of the substrate; etching the substrate on the back side of the substrate to remove at least a portion of the substrate on the back side; forming a first dielectric layer covering the back side of the substrate and extending away from the front side of the substrate; and forming a through silicon via (TSV) adjacent to the DT capacitor, the TSV extending through the first dielectric layer toward the front side of the substrate.

Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same

One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side and a back side, the substrate including: a deep trench (DT) capacitor within the substrate extending toward the back side of substrate, and a through silicon via (TSV) adjacent to the DT capacitor within the substrate extending toward the back side of the substrate, the TSV including a metal substantially surrounded by a liner layer and an insulating layer substantially surrounding the liner layer; etching the back side of the substrate to expose the TSV on the back side of the substrate; and forming a first dielectric layer covering the exposed TSV on the back side of the substrate and extending away from the front side of the substrate.

The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures with a hermetic seal, and methods of manufacture. The structure includes: a guard ring structure surrounding an active region of an integrated circuit chip; an opening formed in the guard ring structure; and a hermetic seal encapsulating the opening and a portion of the guard ring structure, the hermetic seal being structured to prevent moisture ingress to the active region of the integrated circuit chip through the opening.

Corrosion resistant chip sidewall connection with crackstop and hermetic seal

The disclosure generally relates to semiconductor structures and, more particularly, to electrical connections used with crackstop structures and methods of manufacture. The structure includes: a conductive material; a dielectric material formed over the conductive material; a non-corrosive conductive material in at least one opening of the dielectric material and in direct contact with the conductive material; a crackstop structure formed over the dielectric material; and at least one of wiring layer in contact with the non-corrosive conductive material.

Electrical connection around a crackstop structure

SOI wafers with buried dielectric layers to prevent Cu diffusion

The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility.

Metal to metal bonding for stacked (3D) integrated circuits

Wafer to wafer alignment which includes a first semiconductor wafer and a second semiconductor wafer. The first and second semiconductor wafers have selectively-activated alignment arrays for aligning the first semiconductor wafer with the second semiconductor wafer. Each of the alignment arrays include an alignment structure which includes an antenna connected to a semiconductor device. The antenna in each of the alignment arrays is selectively activated to act as a charge source or as a charge sensing receptor. The alignment arrays are located in the kerf areas of the semiconductor wafers. The semiconductor wafers are aligned when the charge sources on one semiconductor wafer match with the charge sensing receptors on the other semiconductor wafer.

Wafer to wafer alignment

Growing community of inventors

Poughkeepsie, NY, United States of America

John Anthony Fitzsimmons