International Business Machines Corporation

John Anthony Bracchitta

Wilbur David Pricer

Tak H Ning

Jed Hickory Rankin

James William Adkisson

Kerry Bernstein

William J Cote

Jack Allan Mandelman

Mark David Jaffe

Mark Alan Lavin

Eric Jeffrey White

James Spiros Nakos

Matthew R Wordeman

Daniel Nelson Maynard

Stephen A Parke

Edward W Sengle

Anthony K Stamper

Effendi Leobandung

John J Ellis-Monaghan

Kirk David Peterson

Jerome Brett Lasky

Bernadette Ann Pierson

Henry Charles Rickers

Howard J Walter, Jr

Jeffrey Bowman Johnson

Randy William Mann

Michel S Michail

Glen L Miles

Anthony C Speranza

Jeffrey H Oppold

Stephen A Mongeon

Patricia McGuiness Marmillion

Patricia McGuinness Marmillion

Gabriel Hartstein

An intellectual property management facility for proactively creating, developing and managing an intellectual property portfolio includes: determining available resource capacity for an intellectual property activity in a tracking system; assigning technical attributes to the activity in the tracking system; apportioning resource capacity for the activity by technical attribute based on the value assigned to each of the technical attributes and based on available resource capacity; obtaining actual resource usage by technical attribute from the tracking system; and managing resource allocation for the intellectual property activity by determining the difference between the actual resource usage and the resource allocation by technical attribute.

Intellectual property management method and apparatus

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

Method of manufacturing an intralevel decoupling capacitor

A process for forming capacitors in a semiconductor device. In one embodiment, a first insulating layer is deposited on the semiconductor device; a trench is formed in the insulating layer; a first low resistance metal layer is formed covering the interior surface of the trench; a first polysilicon layer is formed over the first low resistance metal layer; a first dielectric layer is formed over the first polysilicon layer; a second polysilicon layer is formed over the first dielectric layer; a second low resistance metal layer is formed over the second polysilicon layer; a third polysilicon layer is formed over the second low resistance metal layer; a second dielectric layer is formed over the third polysilicon layer; a fourth polysilicon layer is formed over the second dielectric layer; a third low resistance metal layer is formed over the fourth polysilicon layer until the trench is filled; the semiconductor device is planarized until the first, second and third low resistance metal layers are exposed above the trench; finally, capacitor leads are formed to the first, second, and third low resistance metal layers.

Polysilicon capacitor having large capacitance and low resistance

A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

Double planar gated SOI MOSFET structure

A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.

Three device DRAM cell with integrated capacitor and local interconnect

A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Trench isolation for active areas and first level conductors

A field effect floating gate transistor forming an NVRAM cell is disclosed. A substrate having field isolation structures includes therebetween a doped region forming a channel connecting a source and drain. An oxide layer is disposed over said channel forming a tunneling oxide layer for the device. A layer of polysilicon extends over the oxide layer, to each of the isolation structures and then extends upwards forming a U-shaped pillar floating gate. A second oxide layer disposed within the interior of the U-shaped floating gate supports a control gate. A second layer of polysilicon formed over the second oxide layer forms a control gate, and is connected to a conductor which is common to a row of such cells within a memory. The control gate is coupled to the floating gate through the second oxide layer to the upwardly extending layer of the floating gate as well as over the portion of the floating gate extending over the channel.

NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell area

A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N and P diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N diffusion to said P diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P diffusion is formed in the N well in the pillar adjacent the distal end and a N diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

Method for forming pillar CMOS

A non-volatile random access memory (NVRAM) cell and methods of forming thereof are disclosed. The NVRAM cell includes a substrate having source and drain regions. A spike having a sharp tip extends in the source region. Instead of a single spike, two adjacent spikes are included in the source. Alternatively, in addition to the single spike in the source, two adjacent spikes are included in the drain. The two adjacent spikes have one tip pointing toward the floating gate and two tips pointing away from the floating gate. The spikes provide high electric field to facilitate charge movement between the floating gate and the source region. A tunnel oxide layer separates the floating gate from the substrate. A gate oxide and a control gate are also formed over the floating gate. The single spike is formed by preferentially etching the substrate along a selected crystal plane through an opening formed in a mask that covers the substrate. The two adjacent spikes are formed by first forming spacers on sidewalls of the opening to reduce a width thereof; filling the reduced opening with a mask plug; removing the sidewalls; and etching the substrate.

Method of fabricating a non-volatile semiconductor device

Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitor

Growing community of inventors

South Burlington, VT, United States of America

John Anthony Bracchitta