International Business Machines Corporation

John Andrew Schumann

Debapriya Chatterjee

Karen E Yokum

Bryant Cockcroft

Shakti Kapoor

Tharunachalam Pindicura

Kevin Barnett

Larry Scott Leitner

Paul Frank Lecocq

Vivek Britto

Paul Umbarger

Manoj Dusanapudi

Jeffrey W Kellington

Shricharan Srivatsan

Lawrence Leitner

Lance G Hehenberger

Jamory Hawkins

Aishwarya Dhandapani

Rahul Batra

John Charles Goss

Omesh Bajaj

Christopher R Jones

Christopher M Riedl

Brian William Thompto

Prabhakar Nandavar Kudva

Vitali Sokhin

Amir Nahir

Gil Eliezer Shurek

Wisam Kadry

Naoko Pia Sanda

Shimon Landa

Yan Xia

Dimtry Krestyashyn

Wallace Sharp

Madhumitha Venkataraman

Piriya K Hall

A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

Method for latency detection on a hardware simulation accelerator

A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated it is provided to the hypervisor.

Obscuring information in virtualization environment

Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.

Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation

A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Method and system for detection of thread stall

A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.

Processor performance monitor that logs reasons for reservation loss

A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

Address translation cache invalidation in a microprocessor

An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.

Identifying translation errors

A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.

Dynamic modification of instructions that do not modify the architectural state of a processor

A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.

Performance benchmark generation

Examples described herein provide a computer-implemented method that includes executing, by the microprocessor, instructions in an instruction stream of the microprocessor. The method further includes triggering, by control logic of the microprocessor, error condition monitoring logic. The method further includes executing, by the error condition monitoring logic of the microprocessor, an error instruction stream built into the microprocessor to break the microprocessor out of an error condition.

Software-invisible interrupt for a microprocessor

A method, computer program product, and computer system are disclosed that in one or more embodiments includes issuing, from an issuing processor in the computer system, an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system and wherein the return marker comprises an instruction to return information to the issuing processor indicating the identity of each processor where an invalidated entry was located. The method, product, and system in an embodiment further includes broadcasting the address translation invalidation instruction with the return marker to one or more storage locations of one or more of the processors in the computer system other than the issuing processor; invalidating the address translation entry corresponding to the broadcasted address translation invalidation instruction; and returning to the issuing processor information on each storage location corresponding to the invalidated address translation entry. In one or more embodiments, the returned information is used to determine the performance of the computing system, identifying the storage locations where data was located.

System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors

A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

Precise verification of a logic problem on a simulation accelerator

Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.

Growing community of inventors

Austin, TX, United States of America

John Andrew Schumann