Luxtera, Inc.

John Andrew Guckenberger

Thierry J Pinguet

Daniel Kucharski

Sherif Abdalla

Attila Mekis

Gianlorenzo Masini

Steffen Gloeckner

Kosei Yokoyama

Subal Sahni

Peter De Dobbelaere

Peter DeDobbelaere

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Method and system for monolithic integration of photonics and electronics in CMOS processes

Methods and systems for eliminating polarization dependence for 45 degree incidence MUX/DEMUX designs may include an optical transceiver, where the optical transceiver comprises an input optical fiber, a beam splitter, and a plurality of thin film filters arranged above corresponding grating couplers in a photonics die. The transceiver may receive an input optical signal comprising different wavelength signals via the input optical fiber, split the input optical signal into signals of first and polarizations using the beam splitter by separating the signals of the second polarization laterally from the signals of the first polarization, communicate the signals of the first polarization and the second polarization to the plurality of thin film filters, and reflect signals of each of the plurality of different wavelength signals to corresponding grating couplers in the photonics die using the thin film filters.

Method and system for eliminating polarization dependence for 45 degree incidence MUX/DEMUX designs

Methods and systems for a narrowband, non-linear optoelectronic receiver are disclosed and may include amplifying a received signal, limiting a bandwidth of the received signal, and restoring the signal utilizing a level restorer, which may include a non-return to zero (NRZ) level restorer. The NRZ level restorer may include a pulse-triggered bistable circuit, which may include two parallel inverters, with one being a feedback path for the other. The inverters may be single-ended or differential. A photogenerated signal may be amplified in the receiver utilizing a transimpedance amplifier and programmable gain amplifiers (PGAs). A received electrical signal may be amplified via PGAs. The bandwidth of the received signal may be limited utilizing one or more of: a low pass filter, a bandpass filter, a high pass filter, a differentiator, or a series capacitance on the chip. The signal may be received from a photodiode integrated on the chip.

Method and system for a narrowband, non-linear optoelectronic receiver

Methods and systems for eliminating polarization dependence for 45 degree incidence MUX/DEMUX designs may include an optical transceiver, where the optical transceiver comprises an input optical fiber, a beam splitter, and a plurality of thin film filters coupled to a photonics die. The thin film filters are arranged above corresponding grating couplers in the photonics die. The transceiver may receive an input optical signal comprising different wavelength signals via the input optical fiber, split the input optical signal into signals of first and polarizations using the beam splitter by separating the signals of the second polarization laterally from the signals of the first polarization, communicate the signals of the first polarization and the second polarization to the plurality of thin film filters, and reflect signals of each of the plurality of different wavelength signals to corresponding grating couplers in the photonics die using the thin film filters.

A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die.

Methods and systems for a narrowband, non-linear optoelectronic receiver are disclosed and may include amplifying a received signal, limiting a bandwidth of the received signal, and restoring the signal utilizing a level restorer, which may include a non-return to zero (NRZ) level restorer comprising two parallel inverters, with one being a feedback path for the other. The inverters may be single-ended or differential. A photogenerated signal may be amplified in the receiver utilizing a transimpedance amplifier and programmable gain amplifiers (PGAs). A received electrical signal may be amplified via PGAs. The bandwidth of the received signal may be limited utilizing one or more of: a low pass filter, a bandpass filter, a high pass filter, a differentiator, or a series capacitance on the chip. The signal may be received from a photodiode integrated on the chip, where the photodiode may be AC coupled to an amplifier for the amplifying.

A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Method and system for implementing high-speed interfaces between semiconductor dies in optical communication systems

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Monolithic integration of photonics and electronics in CMOS processes

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

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San Diego, CA, United States of America

John Andrew Guckenberger