Memc Electronic Materials, Inc.

Globalwafers Co., Ltd.

Sunedison Semiconductor Limited (uen201334164h)

Sunedison Semiconductor Limited

John Allen Pitney

Robert J Falster

Vladimir V Voronkov

Peter D Albrecht

Manabu Hamano

Shawn George Thomas

Lu Fei

Lance G Hellwig

Arash Abedijaberi

Thomas A Torack

Ichiro Yoshimura

Sumeet S Bhagavat

Srikanth Kommu

Lawrence P Flannery

Khiam How Low

Ichiron Yoshimura

Swapnil Y Dhumal

Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.

Apparatus for stressing semiconductor substrates

A susceptor supports a semiconductor wafer and includes a substantially cylindrical body comprising an outer rim having an upper surface. The body also includes a recess extending into the body from the upper surface to a recess floor such that the recess is sized and shaped for receiving the wafer therein. The body further includes a ledge extending between the rim and the recess floor. The ledge includes a ramp comprising a first surface, a second surface, and a third surface. The first surface is oriented at a first angle with respect to the upper surface; the second surface is oriented at a second angle oriented with respect to the upper surface; and the third surface is oriented at a third angle with respect to the upper surface. Further, the second angle is greater than the first angle.

Epitaxy reactor and susceptor system for improved epitaxial wafer flatness

A system for depositing a layer on a substrate includes a processing chamber including a gas inlet, a plurality of gas flow controllers connected in fluid communication with a gas supply source, a gas distribution plate disposed between the plurality of gas flow controllers and the gas inlet, and a gas injection cap connected in fluid communication between the plurality of gas flow controllers and the gas distribution plate. The gas distribution plate defines a plurality of holes, and the gas injection cap defines a plurality of gas flow passages, each extending from an inlet connected to one of the gas flow controllers to an outlet connected in fluid communication with at least one of the holes in the gas distribution plate. Each of the gas flow controllers is disposed proximate to the gas injection cap.

Substrate processing systems having multiple gas flow controllers

Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.

Processes and apparatus for preparing heterostructures with reduced strain by radial compression

Processes and apparatus for preparing heterostructures with reduced strain by radial distension

Apparatus and methods for wafer processes such as etching and chemical vapor deposition processes are disclosed. In some embodiments, the apparatus includes a susceptor and a ring disposed beneath the susceptor to influence a thickness of the deposited epitaxial layer.

Susceptor assemblies for supporting wafers in a reactor apparatus

In one aspect, a system for depositing a layer on a substrate is provided. The system includes a processing chamber, a gas injecting port, a gas distribution plate, and a plug. The gas injecting port is disposed upstream from the processing chamber. The gas distribution plate is disposed between the gas injecting port and the processing chamber, and includes an elongate planar body and an array of holes therein. The plug is sized to be received within one of the holes, and includes an orifice therethrough for permitting the passage of gas. The plug is capable of being removably secured to the gas distribution plate within one of the holes.

Gas distribution plate for chemical vapor deposition systems and methods of using same

A method of polishing a wafer is disclosed that includes determining a removal profile. The wafer is measured to determine a starting wafer profile and then the wafer is polished. The wafer is again measured after being polished to determine a polished wafer profile. The starting wafer profile and the polished wafer profile are compared to each other to determine the removal profile by computing the amount and shape of material removed from the first wafer during polishing.

Single side polishing using shape matching

A system for depositing a layer on a substrate includes a processing chamber, a gas injecting port for introducing gas into the system, a gas distribution plate disposed between the gas injecting port and the processing chamber, the gas distribution plate including holes therein, and an inject insert liner assembly received within the system adjacent to the gas distribution plate and upstream from the processing chamber. The inject insert liner assembly defines gas flow channels therein extending along a lengthwise direction of the system, wherein each channel includes an inlet and an outlet, and at least one channel is tapered along the lengthwise direction of the system in at least one of a vertical or horizontal direction. The inject insert liner assembly has the same number of gas flow channels as the number of holes in the gas distribution plate.

Inject insert liner assemblies for chemical vapor deposition systems and methods of using same

A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.

Methods for fabricating a semiconductor wafer processing device

The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided.

Growing community of inventors

St. Peters, MO, United States of America

John Allen Pitney