Massachusetts Institute of Technology

Analog Devices,inc.

John A Yasaitis

Jack I Raffel

Glenn H Chapman

Michael W Judy

Maurice S Karpman

Lawrence E Felton

Colin Stephen Gormley

Chang-Han Yun

Mark L Naiman

Lionel Cooper Kimerling

Dong Pan

Jurgen Michel

Jifeng Liu

James A Burns

A method of forming a low loss crystal quality waveguide is provided. The method includes providing a substrate and forming a dielectric layer on the substrate. A channel is formed by etching a portion of the dielectric layer. A selective growth of a Si Ge, or SiGe layer is performed in the area that defines the channel. Furthermore, the method includes thermally annealing the waveguide at a defined temperature range.

Method of fabricating Ge or SiGe/Si waveguide or photonic crystal structures by selective growth

A light conversion apparatus has a germanium-based photodiode, and a polysilicon-based receiving electrode for receiving light to be converted by the photodiode. The receiving electrode is coupled with the photodiode and permits the received light to substantially pass through it to the photodiode. The photodiode is capable of converting the received light into an electrical signal.

Light conversion apparatus with topside electrode

A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Fabricating complex micro-electromechanical systems using a flip bonding technique

An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.

Fabricating integrated micro-electromechanical systems using an intermediate electrode layer

An integrated-circuit (IC) chip formed with a capacitor comprising a lower layer of polysilicon clad with a thin film of TiSi.sub.2 serving as the lower plate of the capacitor, a layer of dielectric, a thin film of titanium nitride (TiN) on the upper surface of the dielectric to serve as the upper plate of the capacitor, a second layer of polysilicon (doped with phosphorous) over the TiN film, and metallization to make contact with the top plate of the capacitor.

Integrated circuit chip formed with a capacitor having a low voltage

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer and a second metal layer. Diffusion barrier may be employed between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Method of forming conductive path by low power laser pulse

In a semiconductor device fabrication process, the SILO (Sealed Interface Local Oxidation) field oxide formation process is used to provide essentially vertical sidewalls between the field oxide surface and active regions. After field oxide formation and doping of active regions, the device is conformally coated with an oxide layer, which is patterned by a conventional photomasking process to define contact holes. Contact holes are then anisotropically etched through the oxide layer to the active regions. Conformal coating of the vertical sidewalls insures that an oxide sidewall spacer remains where the contact holes intersect the field oxide. Finally, a metal contact layer is deposited in the contact holes. The sidewall spacer automatically spaces the metal contact from the edges of the active region, thereby preventing leakage to the substrate.

Partially self-aligned metal contact process

A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

Method and apparatus for forming low resistance lateral links in a

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer, a second metal layer and diffusion barrier layers between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Method of making a conductive path in multi-layer metal structures by

An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a 'flat-band' portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.

Capacitor memory and methods for reading, writing, and fabricating

An improved method for reading metal dual insulator semiconductor capacitor memories is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. According to the invention, a small variable voltage is applied across a selected cell or cells. The range of voltage includes a 'flat-band' portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. The unselected cells are maintained in a depletion state in which their capacitance is a minimum. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell.

Growing community of inventors

Lexington, MA, United States of America

John A Yasaitis