International Business Machines Corporation

Other

John A Voltin

Michael Terrell Vanover

Rajan Krishnamurty

Charles Ray Johns

Robert John Urquhart

John Fred Spannaus

Harrell Hoffman

Charles G Wright

Jimmie Darius Edrington

Dzung Q Vu

Thomas J Ashford

Scott M Smith

Irene Beattie

Narendra Maganlal Desai

Mamata Misra

A frame buffer system includes a first frame buffer containing a first set of pixels, and a second frame buffer containing a second set of pixels. A first register is connected to an output of the first frame buffer, wherein the first register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A second register is connected to an output of the second frame buffer, wherein the second register a number of pixels is stored in which a group of bytes of data is stored for each of the number of pixels. A selection logic is connected to the first frame buffer and to the second frame buffer. The selection logic selectively selects pixels to be read from the first frame buffer and the second frame buffer into the first register and the second register. A multiplexer has a first input connected to an output of the first register, a second input connected to an output of the second register, and an output configured for connection to a digital to analog converter. The first multiplexer selectively reads the number of pixels from the first register and the second register and a portion of the group of bytes of data for each pixel.

Method and apparatus for display refresh using multiple frame buffers in a data processing system

A pixel merge apparatus and method has been implemented. Included is a configurable graphics device, which may serve as a standalone graphics engine, or as a master or slave in a master/slave configuration. In stand alone mode, the mechanism drives a display device with native pixel data. A device configured in master mode is operable for receiving pixel data from a corresponding slave device, and merging the slave pixel data with native pixel data generated by a rasterizer within the ASIC. Data is communicated between slave and master using a digital data link which may also serve to drive a flat panel display in standalone mode. A FIFO, active in the master, mediates the transfer of the slave pixel data and permits switching between native and slave pixel data with signal pixel resolution. Pixel data may be merged on a frame-by-frame basis, or in split frame mode wherein a first portion of the graphic shown on a display device constitutes native pixels generated in the rasterizer corresponding to the master device, and a second portion of the displayed graphic includes pixels generated by the rasterizer in the slave device.

Pixel data merging apparatus and method therefor

Apparatus and methods for selectively controlling by window the number of overlay planes, the number of overlay palettes, and the overlay/underlay plane masks in a graphics video display system. A logic/multiplex control translates overlay and underlay data patterns from a multiple plane VRAM (Video Random Access Memory), referenced to the graphics system frame buffer, into window specific patterns. The window related translation is conveyed to conventional RAMDACs (Random Access Memory Digital-to-Analog Converters) for raster scan synchronized digital-to-analog conversion. The translation as provided by the controller is responsive to data selectively and dynamically written into a random access memory, thus providing translation of overlay/underlay data into window distinct and selective overlay/underlay palette functions.

Selective control of window related overlays and underlays

In a data processing system, a method for performing a series of operation sequence results and providing such results including the steps of (1) computing the results for each sequence of operations consecutively and (2) reading the results for the proceeding computations during the computation of a current operation result. This method further includes the use of registers for the temporary storage of the sequence results. During the computation of the operation sequence results, other registers are used in performing the sequence operations. The operations store parameters in a progressive fashion. In other words, the initial operations are performed in one set of registers while the final result from the sequence operation is stored in a different register. The result of a previous operation sequence computation is read from a register that is not being used during the computation of the current sequence operation. Also, included is an interlock capability to prevent the storing of sequence in registers that are concurrently being read.

Floating point apparatus with concurrent input/output operations

A data processing system including a processor that executes a plurality of instructions including at least one instruction that requires an external operation to be performed. The processor provides information for this external operation instruction to an external device and continues to execute instructions that do not require the results from this external operation. The external device receives the information from the processor, performs the external operation and provides the results to the processor. A further aspect of this data processing system is an interface that is interconnected between the processor and the external device. The processor provides the external operation information to the interface. The interface in turn provides the information to the external device and concurrently accesses data from the memory that will be required by the external device for performing the external operation.

Processor controlled DMA controller for transferring instruction and

Apparatus is provided for the safeguarding of data recorded on disk and diskettes by tunnel erase magnetic head assembly which comprise a read/write transducer for magnetically recording data along tracks on said disk and a pair of magnetic erase transducers adjacent to the read/write transducer for limiting the width of the recorded data. The apparatus for safeguarding the recorded data comprises apparatus for sensing the activation of the erase and/or read/write transducer and apparatus responsive to such sensed activation for determining if the activation is erroneous.

Safeguarding of data recorded on disk by tunnel erase magnetic head

In a system for controlling a machine tool by a tool controller under the supervision of a central data processor, in which the controller transforms the data provided by the central processor into a format compatible with the machine tool, e.g., clock pulse encoded data format suitable for writing into and reading out of a serial storage magnetic memory device, a test system is provided wherein the central processor includes a simulation of the controller. This simulated controller gives the processor the capability of simulating and applying to the tool controller data in a format equivalent to that normally applied to the tool controller from the tool itself, e.g., a clock encoded data read output. The simulated controller also provides the central processor with the capability of receiving from the tool controller a tool control output in the format compatible with the control tool, e.g., clock encoded data and changing said data into an original format usable in the central processor.

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Austin, TX, United States of America

John A Voltin