Micron Technology Incorporated

Zilog, Inc.

Boise Technology, Inc.

John A Smythe

Gurtej S Sandhu

Bhaskar Srinivasan

Scott E Sills

Nishant Sinha

Si-Woo Lee

Neil Joseph Greeley

Ming Zhang

Joseph Neil Greeley

Jigish D Trivedi

Armin Saeedi Vahdat

Roy Edward Meade

Timothy A Quick

Janos Fucsko

Sumeet C Pandey

Lei Bi

Sony Varghese

Sanh D Tang

Haitao Liu

Li Li

Chris M Carlson

Richard J Hill

Vishwanath Bhat

Stefan Uhlenbrock

Rishikesh Krishnan

Noel Rocklein

John Eugene Berg

Francois H Fabreguette

Marko Milojevic

Chandra V Mouli

Kamal M Karda

Fatma Arzum Simsek-Ege

Witold Kula

Mark W Kiehlbauch

Brenda D Kraus

Scott L Light

Deepak Chandra Pandey

Kevin L Beaman

Steve Kramer

William Budge

Grady S Waldo

Robert D Patraw

Ken Tokashiki

Timothy K Carns

Bernice L Kickel

Jeff Hull

Durai Vishak Nirmal Ramaswamy

Kunal R Parekh

Vassil N Antonov

Brett D Lowe

Hyun Sik Kim

John David Hopkins

Yongjun Jeff Hu

Eugene P Marsh

Michael P Violette

Jordan D Greenlee

Shyam Surthi

Everett Allen McTeer

Neal R Rueger

Shuang Meng

David K Hwang

Matthew N Rocklein

Silvia Borsari

Zailong Bian

John F Kaeding

Byeung Chul Kim

Brian J Coppa

John A Ransom

Paul A Paduano

Woohee Kim

Sutharsan Ketharanathan

Glen H Walters

Scott Sllls

Jeff Hall

Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for memory arrays. One example method includes forming logic circuitry on a silicon substrate in a first working surface and depositing an isolation material on the first working surface to encapsulate the logic circuitry and to form a second working surface above the first working surface. Further, the example method includes etching the isolation material to form a vertical opening through the isolation material and epitaxially growing single crystalline silicon from the silicon substrate and horizontally on the second working surface in a first, a second, and a third direction to cover the second working surface. The example method further includes removing a portion of the epitaxially grown single crystalline silicon to partition distinct and separate third working surface areas in which to form memory cell components and forming storage nodes above the memory cell components.

Epitaxial single crystalline silicon growth for memory arrays

Systems, methods, and apparatuses are provided for epitaxial single crystalline silicon growth for a horizontal access device. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes selectively removing first portions of the semiconductor material from the second vertical openings to form horizontal openings with a remaining second portion of the semiconductor material at a distal end of the horizontal openings from the second vertical openings, and epitaxially growing single crystalline silicon within the horizontal openings from the distal end of the horizontal openings toward the second vertical openings to fill the horizontal openings.

Epitaxial single crystalline silicon growth for a horizontal access device

An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

Channel conduction in semiconductor devices

Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Methods of forming material within openings extending into a semiconductor construction, and semiconductor constructions having fluorocarbon material

A transistor comprising a channel region on a material is disclosed. The channel region comprises a two-dimensional material comprising opposing sidewalls and oriented perpendicular to the material. A gate dielectric is on the two-dimensional material and gates are on the gate dielectric. Semiconductor devices and systems including at least one transistor are disclosed, as well as methods of forming a semiconductor device.

Transistors comprising two-dimensional materials and related memory cells and electronic devices

A method of forming a structure comprises forming a pattern of elongate features extending vertically from a base structure. Conductive material is formed on the elongate features. After completing the forming of the pattern of elongate features, the elongate features, the conductive material, or both is (are) exposed to at least one surface treatment gas. The at least one surface treatment gas comprises at least one species formulated to diminish attractive or cohesive forces at a surface of the conductive material. Apparatus and additional methods are also described.

Methods for inhibiting line bending during conductive material deposition, and related apparatus

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0° C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0° C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

Methods of forming high aspect ratio features

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

Microelectronic devices including conductive rails, and related methods

Methods of forming silicon nitride. Silicon nitride is formed on a substrate by atomic layer deposition at a temperature of less than or equal to about 275&#xb0; C. The as-formed silicon nitride is exposed to a plasma. The silicon nitride may be formed as a portion of silicon nitride and at least one other portion of silicon nitride. The portion of silicon nitride and the at least one other portion of silicon nitride may be exposed to a plasma treatment. Methods of forming a semiconductor structure are also disclosed, as are semiconductor structures and silicon precursors.

Methods of forming silicon nitride including plasma exposure

Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation. Subsequently, the photopatternable dielectric material is developed to pattern the photopatternable dielectric material into a first dielectric structure which at least partially fills the opening, and to remove the photopatternable dielectric material from over the upper surface.

Semiconductor constructions comprising dielectric material, and methods of forming dielectric fill within openings extending into semiconductor constructions

Systems, methods and apparatus are provided for a three-node access device in vertical three dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. An etchant process is used to form a first vertical opening exposing vertical sidewalls in the vertical stack adjacent a first region. The first region is selectively etched to form a first horizontal opening removing the sacrificial material a first horizontal distance back from the first vertical opening. A first source/drain material, a replacement channel material having backchannel passivation, and a second source/drain material are deposited in the first horizontal opening to form the three-node access device for a memory cell among the arrays of vertically stacked memory cells.

Channel integration in a three-node access device for vertical three dimensional (3D) memory

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0&#xb0; C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0&#xb0; C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

Methods of forming high aspect ratio openings and methods of forming high aspect ratio features

A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.

Integrated circuity, dram circuitry, methods used in forming integrated circuitry, and methods used in forming DRAM circuitry

Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material. Selectively removing the sacrificial material in the first region to form first horizontal openings. Repairing a second side of the gate dielectric exposed where the sacrificial material was removed in the first region. Depositing a first source/drain region, a channel region, and a second source/drain region in the first horizontal openings.

Gate dielectric repair on three-node access device formation for vertical three-dimensional (3D) memory

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Boise, ID, United States of America

John A Smythe