U.S. Philips Corporation

John A Slatter

David J Coe

Henry E Brockman

John M Shannon

Jan Haisma

Kenneth R Whight

David H Paxman

David C Yule

A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5). Means are provided for transmitting light into the semiconductor body via the given surface to enable photogeneration of charge carriers in the vicinity of the photosensitive pn junction(s) (17). The further region(s) may include one or more annular floating regions (6') spaced apart from the main pn junction(s) and each other.

Photosensitive device suitable for high voltage operation

A semiconductor body (100) has a first device region (20) of one conductivity type forming with a second device region (13) of the opposite conductivity type provided adjacent one major surface (11) of the semiconductor body (100) a first pn junction (40) which is reverse-biassed in at least one mode of operation. A floating further region (50) of the opposite conductivity type is provided within the first device region (20) remote from the major surfaces (11 and 12) of the semiconductor body (100) and spaced from the second device region (13) so that, in the one mode, the depletion region of the first pn junction (40) reaches the floating further region (50) before the first pn junction (40) breaks down. The floating further region (50) forms a further pn junction (51) with a highly doped capping region (60) of the one conductivity type which is provided within the first device region (20) between the floating further region (50) and the second device region (13) and spaced from the second device region (13) and which enables a high electric field to exist between the first pn junction (40) and the further floating region (50) with less risk of the device breaking down.

Semiconductor device having high breakdown voltage

A semiconductor device (10) is formed by providing first and second semiconductor bodies (1 and 11) each having first and second major surfaces (2 and 3) and (12 and 13), respectively, defining a rectifying junction pattern (21) adjacent to at least one (12) of the first major surfaces, and bonding the first major surfaces (2 and 12) together to join the two semiconductor bodies (1 and 11) to form the semiconductor device (10) in which the rectifying junction pattern 21 defines a path for the flow of charge carriers between the second major surfaces. The rectifying junction pattern (21) is defined at the one first major surface (12) by an electrically conductive pattern (20) forming a Schottky junction (21) with at least one of the first and second semiconductor bodies (1 and 11).

Method of manufacturing a semiconductor device including a static

A semiconductor body (1) has a portion (2a) of one conductivity type adjacent one major surface (3). A first active device region (4) forms with the portion (2a) a first pn junction (5) which terminates at the one major surface (3) and is reverse-biassed in at least one mode of operation of the device. A second active device region (6) provided within the first active device region (4) forms with the first active device region (4) a second pn junction (7) terminating at the one major surface (3). One or more further regions (8) of the opposite conductivity type are provided with the portion (2a) adjacent the one major surface (3) surrounding and spaced from the first pn junction (5) to lie within the spread of the depletion region when the first pn junction (5) is reverse-biased in the at least one mode of operation. An additional region (9) of the opposite conductivity type is provided between and spaced from the first pn junction (5) and an inner one (8a) of the further regions (8), and an electrical connection (10) is provided between the additional region (9) and the second active device region (6) to provide a path for the flow of charge carriers between the further regions (8) and the second device region (6).

Semiconductor device having increased breakdown voltage

A semiconductor device includes a bipolar transistor having an emitter region of one conductivity type formed in a base region of the opposite conductivity type, the base region being provided in a collector region of the one conductivity type. A first insulated gate field effect transistor provides a gateable connection to the emitter region of the bipolar transistor while a second insulated gate field effect transistor provides a charge extraction path from the base region when the bipolar transistor is turned off. The first insulated gate field effect transistor includes a further region of the other conductivity type provided in the emitter region, and a source region of the one conductivity type formed in the further region and an insulated gate overlying a channel area comprising at least part of the further region to provide a gateable connection between the emitter region and the source region of the first insulated gate field effect transistor. The second insulated gate field effect transistor having an insulated gate overlying a channel area comprising at least part of the emitter region adjacent the base region to provide a gateable connection between the base region and a source of the second insulated gate field effect transistor.

Semiconductor devices

Separate areas of an active unipolar barrier, e.g. a Schottky barrier, of a semiconductor device are located between closely-spaced field-relief regions which provide the device with an improved voltage blocking characteristic. The flow of minority carriers into the adjacent body portion under forward bias is restricted by providing, at least at the areas of the field-relief regions, a layer of different material from that of the body portion and from that of the unipolar barrier-forming means. The layer of different material may form a high-impedance electrical connection with the field-relief regions, and/or it may form with the body portion a heterojunction such as, for example, a Schottky barrier of higher barrier height, a barrier between different band gap materials or a MIS structure, which heterojunction forms part of the field-relief regions.

Semiconductor devices having field-relief regions

A gate turn-off PIN diode has its anode and cathode adjacent to the same major surface of the device body. The anode and cathode regions are separated by a recess which extends into the body towards the gate region. Turn-off is effected by the spread of a depletion layer from the reverse-biased gate junction to the recess.

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Crawley Down, United Kingdom

John A Slatter