Precision Monolithics, Inc.

Advanced Micro Devices Corporation

John A Schoeff

Daniel J Dooley

Donald T Comer

A digital-to-analog converter is provided which converts a series of digital binary numbers into an analog signal having an amplitude proportional to the values of the binary numbers. The disclosed embodiment of this invention includes a segment generator having input terminals coupled to receive the most significant digits of the binary numbers to be converted, wherein the segment generator provides a first signal proportional to the values of the most significant digits of the binary numbers. A step generator is also included which receives the remaining lesser significant digits of the binary number and provides a second signal proportional to the values of these lesser significant digits of the same binary numbers. Additionally, means for combining the first and second signals is provided to form an analog signal proportional to the value of the binary number to be converted.

Monolithic digital-to-analog converter

The outputs of individual stages in a digital to analog converter are each trimmed by independent circuitry which includes a plurality of transistors connected to a common output terminal, the physical dimensions of each transistor being scaled in proportion to desired levels of current flow, and selectable switches connected in circuit with each of the transistors. Selectable switches are actuable to produce an output trimming current of a desired magnitude, which current is used to correct the untrimmed stage output. The invention includes circuitry for controlling the polarity of the trimming current relative to the stage, and for selectively expanding or contracting the trimming range to optimize the trimming currents for the particular characteristics of the converter. A favorable balance between trimming accuracy and the area occupied by the trimming circuitry is attained by the use of both emitter-scaled and multicollector transistors in the trimming circuits.

Selectable trimming circuit for use with a digital to analog converter

A digital to analog converter is disclosed wherein two current outputs are provided, one the complement of the other. The digital to analog converter includes a novel two branched, symmetric, transistor switching circuit as well as an improved electrical n-bit weighting network which has ports for communicating weighted signal segments to connected transistor switching circuits. Logic inputs to the switching circuits determine whether an output signal is to be supplied in a first output summing line or a second, complementary, output summing line, both of which have high output impedance and high output voltage compliance which defines true current output.

Digital to analog converter with complementary true current outputs

A symmetric, two-branched transistor switching circuit is disclosed wherein steering current is fed to a node between the two branches. A logic input signal controls the electrical balance between the two branches controlling the flow of steering current from one branch to the other and back, depending upon two discrete logic input levels. The two-branched circuit is connected to a pair of loads, one associated with each circuit branch as well as to a common node which may be connected to an auxiliary circuit. By a balanced circuit configuration and supplying properly regulated bias during a logic input transition, the effects of parasitic capacitance, which normally delays switching times, may be reduced, thereby permitting the switching of very low levels of current, i.e. on the order of 1 or 2 microamperes at speeds comparable to those obtained when switching 1 or 2 ma. An auxiliary circuit which may be connected to the common node of the circuit is an electrical ladder which decrements current. A balanced output is provided in a pair of output lines for supplying an output current I.sub.OUT and its complement I.sub.OUT.

Differential input-differential output transistor switching cell

Disclosed is a multistage resistor and transistor network for use in forming a plurality of weighted signals and which utilizes a conventional R-2R ladder network connected to a single reference means for decrementing the reference signal into weighted signals and a remainder signal. Rather than terminating the remainder, as in the prior art, at least one slave ladder network is connected for receiving the remainder signal and decrementing the remainder signal into a plurality of decrementally weighted signals to be taken in parallel with the decrementally weighted signal segments of a master ladder.

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Los Gatos, CA, United States of America

John A Schoeff