Sun Microsystems, Inc.

Wang Laboratories, Inc.

John A Saba

Martin J Schwartz

Steven W Aiken

Richard Tank-Kong

An interface for transferring data via a PCI bus between a initiator device and a host target having a local cache buffer. The PCI interface to the local cache buffer includes an interface controller, an address resolution unit, data and address logic, byte enable logic and command processing logic. The command and data logics resolve address hits and misses and determine when a write operation will occur to the local cache buffer. The interface controller performs hand shaking operations between the PCI interface and an initiator device connected via the PCI bus. The interface controller also regulates the transfer of data between the device initiator and the local cache buffer, providing status and control signals to the cache controller during a given transfer cycle. The data logic receives the data from the PCI bus and verifies parity providing data and parity information to the cache buffer and cache parity error buffer. The byte enable logic receives and processes byte enable information associated with each data transfer phase and generates start pointer and end pointer information for a determination of the valid data bytes which are stored in a particular cache line. Finally, the interface controller generates an end of line signal upon the completion of a cache line write allowing for the transfer of uniform data blocks across the cache buffer to host boundary.

High speed flexible slave interface for parallel common bus to local

A prefetch unit includes a Branch history table for providing an indication of an occurrence of a Branch instruction having a Target Address that was previously taken. A plurality of Branch mark bits are stored in an instruction queue, on a half word basis, in conjunction with a double word of instruction data that is prefetched from an instruction cache. The Branch Target Address is employed to redirect instruction prefetching. The Branch Target Address is also pipelined and follows the associated Branch instruction through an instruction pipeline. The prefetch unit includes circuitry for automatically self-filling the instruction pipeline. During a Fetch stage a previously generated Virtual Effective Address is applied to a translation buffer to generate a physical address which is used to access a data cache. The translation buffer includes a first and a second translation buffer, with the first translation buffer being a reduced subset of the second. The first translation buffer is probed, during a Generate stage, to prefetch, if possible, the required operand. The prefetch unit further provides 24-bit or 31-bit effective address generation on an instruction by instruction basis.

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Dracut, MA, United States of America

John A Saba