Hughes Aircraft Company

Other

Hrl Laboratories, LLC

John A Roth

Neil A Carter

Peter David Brewer

Lynette B Roth

Mehran Matloubian

Carl W Pobanz

Andrew T Hunter

Terence J De Lyon

Michael G Case

A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.

Process for assembling three-dimensional systems on a chip and structure thus obtained

A method and apparatus for enabling the use of optical techniques for temperature measurement of a semiconducting substrate coated with an optically opaque overlayer. A reflective mirror structure is inserted between the semiconducting substrate and the optically opaque overlayer. The reflective structure prevents the overlayer from absorbing light transmitted through the semiconducting substrate and instead reflects the light, thereby restoring the substrate front-surface reflectivity required for temperature measurement analysis by optical techniques such as absorption edge reflectance spectroscopy.

Method for temperature measurement of semiconducting substrates having

Ultraviolet (UV) light from a lamp (12) or laser (38) is provided for cracking Group V and Group VI species comprising clusters (dimers and tetramers) or metal-organic molecules to form monomers (atoms). The UV radiation interacts with a molecular beam (14) of Group V and Group VI species following their generation in a source cell (16), which may be an effusion source in molecular beam epitaxy (MBE) apparatus, a thermal cracker cell in gas-source MBE apparatus, or a gas injector cell in metal-organic MBE apparatus (MOMBE). As configured, the UV light source and associated elements comprise a unit, termed herein a 'photo-cracker cell' (10). The photo-cracker cell includes an elliptical reflective cavity (18), which defines two foci. The source of UV light is located along one focus and the path of the molecular beam is located along the other focus substantially parallel thereto. The photo-cracker cell may be provided on existing MBE or MOMBE apparatus, between the present source cell and the growth chamber (36) in which III-V, IV, and II-VI semiconductor layers on substrates are deposited.

Photo-cracker cell

A solid waste compactor having multiple waste receptacles for separately receiving, temporarily holding, and compacting separate classes of solid waste, for example paper, glass, aluminum cans and steel cans. In one preferred embodiment there is a single screw-driven compaction ram which compacts solid waste in the several receptacles, which are rotatable into position beneath the ram on a revolving table. In an alternative embodiment there are multiple compaction rams for the multiple receptacles, with all the compaction rams being driven in series by means of a common drive chain, and with the receptacles being mounted on a slidable carriage for removal from the compactor.

Solid waste compactor with multiple receptacles

A solid waste compactor having multiple waste receptacles for separately receiving, temporarily holding and compacting separate classes of solid waste, for example paper, glass, aluminum cans and steel cans. A single screw-driven compaction ram compacts solid waste in the several receptacles. The compaction ram extends from a trolley which is movable in two orthogonal directions on orthogonal tracks positioned above the receptacles. A reversible compaction motor mounted on the trolley drives the compaction ram up and down. The receptacles are mounted on a slidable carriage for removal from the compactor.

The specification discloses a process for forming a superconductor/semiconductor junction structure having optimized low-temperature current transport properties by first providing a substrate of a chosen semiconductor material having an atomically clean surface. A layer of a first chosen superconducting material is deposited on or above the surface of the substrate to a predetermined thickness. Either before or after the formation of this layer of the first superconducting material, a region of a second chosen superconducting material is formed between the surface of the substrate and the layer of the first superconducting material to serve as an interfacial reaction barrier to prevent the reaction between the surface of the substrate and the first chosen superconducting material at the interface thereof which would otherwise result in the formation of an undesired non-superconducting material at the interface. By preventing this undesired interfacial reaction, an optimized low-temperature current transport path is maintained across the interface and certain device performance characteristics can be optimized. Josephson junction superconducting devices and super-Schottky devices may be formed by this disclosed process.

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Ventura, CA, United States of America

John A Roth