National Semiconductor Corporation

Sun Microsystems, Inc.

Burroughs, Inc.

Visic, Inc.

Other

Intel Corporation

John A Reed

Joel A Karp

Ilbok Lee

Charles E Boettcher

Andrew G Varadi

Mohammed E Ul Haq

Peter J Bagnall

Mohammed E Haq

Dennis J Logwood

An apparatus and method are disclosed for switching the arrays of parallel memory data structures upon the detection of defects in a memory storage device. To date, redundancy has been implemented using duplicate arrays connected to laser zappable fuses. The use of laser zappable fuses imposes restrictive technology constraints. In particular, to avoid damage to surrounding circuity when a fuse is 'zapped,' considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The present invention uses only two extra parallel arrays to correct for any open or short defects in a parallel memory data structure, and does it with a nearly constant array length as the original arrays. The redundant arrays as well as the original arrays are connected to toggle switches. Upon encountering any open or short in the one or more data paths, the toggle switches coupled to the open or short are 'flipped' to connect to the adjacent data paths in a cascading fashion. The toggle switches are implemented as steering logic switches having NMOS and PMOS transistors in a CMOS array. The steering logic switches are controlled with a pointer register which can be implemented either by logically decoding the defect area or by actually implementing a shifter which stops when its state reaches the defect.

Method and apparatus for implementing redundancy in parallel memory

The present invention provides apparatus and methods to achieve a high speed bi-CMOS differential amplifier with controlled output voltage swing for use in amplifying low level complementary logic signals. The differential amplifier is comprised of a load current controller and a sense amplifier. The load current controller compares a desired reference voltage to the voltage drop across a simulated load. The load current controller then produces therefrom a bias voltage corresponding to the current which results in a voltage drop equal to the reference voltage. The bias voltage, when applied to the sense amplifier, limits the output of the sense amplifier to a controlled voltage swing of magnitude equal to the reference voltage.

Method and apparatus for high-speed bi-CMOS differential amplifier with

A downhole tool positioned intermediate the mud motor and the drill bit, for reducing the hydro-static head near or around the bit. What is provided is an upper body portion threadably attachable to the mud motor and having an internal shaft with a bore therethrough for allowing mud to flow down the shaft rotatable during the the operation of the tool. The upper body portion further includes a gear member on the outer wall of the shaft for rotatably engaging the pair of upper gear members which imparts rotation to a pair of lower gear members for further imparting rotation to a fan member located in the lower portion of the tool. The lower portion of the tool member is flared to substantially engage the inner wall of the bore, with the interior of the lower flared portion housing the multi-vane fan so that upon rotation of the fan, the mud below the fan member is sucked into the fan through ports in the bottom of the tool, and out of lateral ports in the wall of the lower section, this movement of mud is effectively being 'pulled' off of the bit to decrease the weight of the column of mud at the bit for more effective cutting. A second embodiment would include in the gearing section of the tool a bell gear member for imparting increased rotation to the fan member for more effective lowering of the weight of the mud at the bit.

Apparatus for reducing hydro-static pressure at the drill bit

A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array.

MOS/CMOS memory cell

There is described a CMOS random access memory having memory access circuitry which substantially eliminates substrate noise caused by capacitive coupling of the bit lines to the substrate, and which allows the memory to have equal length access and cycle times. Access circuitry for each column of cells includes a pair of differential bit lines, at least one bit line equalization transistor, and a CMOS sense amp. The sense amp has two p-channel pull-up transistors, each having its source node connected to a common pull-up node, and two n-channel pull-down transistors, each having its source node connected to a common pull-down node. At the beginning of each memory access cycle the differential bit lines are equalized and the common pull-up and pull-down nodes are equalized. Then, substantially simultaneously, the common pull-up node is charged while the common pull-down node is discharged. By making the bit line charging and discharging activities simultaneous, the substrate noise normally generated by bit line to substrate capacitive coupling is virtually eliminated. Furthermore, since bit line precharge is performed at the beginning of each access cycle, rather than between access cycles, the access and cycle times of the memory are equal.

Dynamic ram with reduced substrate noise and equal access and cycle time

A semiconductor memory is comprised of a semiconductor substrate having first and second spaced apart arrays of memory cells disposed thereon. A plurality of first pairs of bit lines couple to the cells of the first array, and a corresponding plurality of second pairs of bit lines couple to the cells of the second array. Disposed between each first pair and corresponding second pair of bit lines is one X sense amplifier. This amplifier includes a set node selectively coupled to one bit line of the first pair and to one bit line of the second pair, and a reset node selectively coupled to the opposite bit lines of the first and second pair for selectively sensing charge on the four bit lines.

X Sense AMP memory

In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a '0' or a '1' accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells. In a preferred embodiment, the buffer line amplifiers comprise source follower amplifiers.

MOS Dynamic random access memory having an improved sensing circuit

In an MOS dynamic random access memory, address input signals are received by individual comparator buffers which generate corresponding individual pairs of complementary address signals in response to respective ones of the input address signals. The pairs of complementary address signals are strobed from the buffers. Each pair of complementary address signals, as strobed from the individual buffers, diverge from a common potential to a pair of stable complementary address signals which are fed to an array of decoder circuits. Each decoder circuit includes an output line which is precharged to a predetermined potential and is selectively discharged in response to the decoded address signals via a plurality of parallel connected decoder transistors. Each decoder transistor includes a gate control electrode for controlling the conduction between first and second other terminals of the respective transistors. The first terminals are connected to the decoder output line. The pairs of complementary address signals are applied between the gate and second terminals of respective ones of the decoder transistors such that as the complementary address signals diverge sufficiently in amplitude to exceed the turn-on threshold of the individual decoder transistors, those transistors will be rendered conductive for discharging the output line of the respective decoded circuit. Thus, the timing for strobing of the decoder circuit is automatically obtained by the pairs of complementary output signals of the respective address buffers and these address signals need not be held at any predetermined voltage during precharging of the respective decoder output line.

MOS dynamic random access memory having an improved address decoder

This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective columns by source followers and leads from the latch drive write back gates coupled to the respective columns so as to restore a 'zero' level of a cell and also leave a precharged 'one' level with the cell by charging the appropriate column. The respective columns are initially precharged and balanced and then driven by negative going signals.

Ultra high sensitivity sense amplifier for memories employing single

This disclosure relates to memory array organization of single transistor cells and the differential sense amplifiers provided therewith. To accommodate the differential sense amplifiers, the array is laid out in rows and functional columns where a functional column consists of a pair of columns such that odd row cells are connected to the odd column of the pair and even row cells are connected to the even column of the pair. A differential sense amplifier is then provided for each pair of odd and even columns which are inherently balanced at the sense amplifier terminals. Single ended or edge ended I/O circuitry is provided with direct access to the respective pairs of columns.

Interlaced memory matrix array having single transistor cells

An MOS dynamic buffer circuit described in terms of an inverter and used for inverting a timing signal is disclosed. Through the use of bootstrapping, the output from the inverter is equal to the voltage used to drive the inverter without having conduction through the output transistor when the inverter is not supplying an output signal. Thus, the inverter does not require the large amounts of standby power associated with prior art circuits.

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Los Altos, CA, United States of America

John A Reed