Rca Inc.

Harris Corporation

Other

John A Olmstead

Salomon Vulih

Sebastian W Kessler, Jr

Stanley F Wietecha

Thomas D Housten

Harold Allen Wittlinger

Stephen J Glica

Samuel Ponczak

A circuit for generating a bandgap voltage that is insensitive to temperature. The circuit includes an amplifier with a feedback loop having a high impedance output current mirror controlled by transistors connected to an output from the amplifier. The current mirror provides proportional currents to a pair of resistors that are connected to inputs to the amplifier, a first input receiving a temperature sensitive voltage from a first of the resistors, and a second input receiving a voltage that is a combination of a temperature sensitive voltage across a second of the resistors and a temperature sensitive offsetting voltage. The second resistor may be tapped to provide a selectable bandgap voltage. A reference voltage for operating the generator may be obtained from a voltage division of supply voltage by two resistors of the same type.

Temperature insensitive bandgap voltage generator tracking power supply

A circuit for providing an input offset voltage to balance a fully differential amplifier may include two field effect transistors (FETs) in parallel conductive paths for receiving a current, an amplifier current source, a resistor connecting the FETs at their drains, and a second amplifier with inputs for an offset correction voltage and for a reference voltage on which the fully differential amplifier is to be balanced and outputs for providing control inputs to the FETs. The input offset voltage for balancing the fully differential amplifier is the difference between currents in the parallel paths times the resistance of the resistor. The circuit may be used to balance a fully differential amplifier in a telephone CODEC. The correction voltage may correct the total offset from the CODEC, or the offset introduced by a sign bit integrator that provides a correction for excursions of the same polarity in the CODEC.

Offset adjustment for fully differential amplifiers

A sign bit integrator and method for generating a signal to correct an offset in a signal processing system that can distort the output from the system. A charge pulse is generated when the sign of a input signal is sampled in order to provide an offset correction signal with a polarity opposite that of offsets in the system. The charge pulse is provided to a pair of transistors whose size ratio sets the magnitude of the charge pulse. The polarity of the charge pulse is set responsive to a sign bit in the input signal. An integrator capacitor provides the offset correction signal to the signal processing system. A third transistor may be switchably substituted for one of the pair of transistors to change the ratio of sizes and thus change the magnitude of the charge pulse to thereby change the speed with which the offset correction is made. The sign bit integrator and method may be used to correct distortion in a voice signal in a telephone system.

Sign bit integrator and method

An amplifier system embodying the invention includes an input stage comprising one or more differential amplifiers having a high degree of common mode rejection. The inputs of the differential amplifiers of the input stage are AC coupled to different signal input terminals which are adapted to receive small information signals riding on large common mode signals. The AC coupling blocks any dc level associated with the input signals from affecting the amplifier system and the high degree of common mode rejection maintains the gain of the amplifiers relatively constant over a wide range of common mode signals. The outputs of the differential amplifiers of the input stage are connected in common to an output node to sum their output signals and to reduce random noise associated with the input signals and the input stage. The output node of the input stage is AC coupled to the input of a second stage whose output is in turn AC coupled to a third output stage to reduce the effect of amplifier offsets. The gain of the amplifier system is controlled by low pass filters connected to the output node of the input stage and to the output of the second stage. In certain embodiments a biasing clock is coupled via resistors to the inputs of the differential amplifiers to generate a dc bias level at their inputs which is a function of the duty cycle of the clock, the resistor connected at the input and coupling capacitor connected to the input.

Amplifier system for low level sensor signal

A differential amplifier embodying the invention includes a differential stage whose total output current is sensed and whose 'tail' and output current is maintained relatively constant over a large common mode voltage range by means of a current feedback loop. This feature eenables the differential amplifier to accurately amplify low amplitude signals riding on a very large common mode signal. The tail current to the differential amplifier is supplied by a controllable current source. The tail current flows via two differentially connected transistors in two differential output terminals and is divided between them as a function of the voltage applied to two differential signal input terminals. The amplitude of the tail current is set by a current level setting current source connected to a summing node. An amplifier and current mirroring network is connected between the summing node and the controllable current source. A current sensing and mirroring network is connected to the two differential outputs for sensing the total current flowing and feeding back a current proportional thereto to the summing node for maintaining the tail current relatively constant over wide variations in the voltage applied to the signal input terminals.

Amplifier with high common mode rejection

An amplifier includes first and second amplifying stages with the first amplifying stage having an inverting input, a non-inverting input and an intermediate output node at which is produced a signal responsive to signals applied to the inverting and non-inverting inputs. The second amplifying stage has an input connected to the intermediate output node and an output connected to an amplifier output terminal. A selectively enabled transmission gate is connected in series with a capacitor between the input and the output of the second amplifying stage. The selectively enabled transmission gate means, when enabled, functions as a resistance which in combination with the capacitor provides frequency compensation for the amplifier. When the transmission gate is disabled, it functions to disconnect one side of the capacitor and eliminates its loading effect on the amplifier stage.

Comparator amplifier

First and second outputs of a differential amplifier stage are coupled via first and second selectively enabled transmission gates to first and second inputs of a selectively enabled complementary flip-flop. During a data sensing and acquisition phase, the transmission gates are enabled and the flip-flop is disabled. Although the flip-flop is disabled, two of its cross coupled transistors are coupled via the transmission gates to the differential amplifier stage. This enhances the setting of the flip-flop when it is subsequently enabled and the transmission gates are disabled.

Latching comparator employing transfer gates

A comparator circuit includes first and second differential amplifier input stages to which are applied the same differential input signals with each stage being powered by first (V1) and second (V2) operating potentials. The first stage is only responsive to differential input signals ranging in value between V1 and a first state threshold voltage (V.sub.T1) above V2. The second state is only responsive to differential input signals ranging in value between V2 and a second state threshold (V.sub.T2) below V1. Each one of the first and second stages, when operative, produces output signals which can swing fully between V1 and V2 as a function of the input signals. The output signals of the first and second stages are combined in an OR'ing circuit to produce an output signal whose amplitude can swing over the full operating voltage applied to the first and second supply lines for values of differential input signals ranging between V1 and V2.

Full range input/output comparator

The output of a digital-to-analog (D/A) converter is coupled to the input of a filter. The D/A converter is initialized each time a new digital word is applied to the D/A converter for conversion, whereby each data conversion cycle (T.sub.D) includes an initialization interval (T.sub.I) followed by a conversion interval (T.sub.C). During T.sub.I the output of the D/A converter is driven to a reference level and during T.sub.C to the output of the D/A converter corresponds to the value of the input signal. The input section of the filter stores the D/A output just prior to initialization and, for during T.sub.I, coupling the stored value within the filter for processing while inhibiting the coupling to the filter of the reference level present at the D/A output.

Switched capacitor filter for use with a digital-to-analog (D/A)

The present invention involves a geometric structure for a pair of matched capacitors for use in an integrated circuit device. Each of the matched capacitors are composed of at least one of a unit capacitor and one or more subcapacitors arranged in abutting relationship. Each subcapacitor includes a tab projecting outwardly and an opening of similar size projecting inwardly. The tab is arranged to abut against the side of a unit capacitor or another subcapacitor. The tabs and openings are sized so that the area to peripheral length ratios of the matched capacitors are identical.

Constant ratio, size insensitive, capacitor structure

A diode structure is disclosed wherein the diode includes a body of a first type conductivity material; a first region of a second conductivity material in the body and having an opening therein through which a portion of the body projects; and a second region of the first conductivity material in the portion of the body that projects through the opening. The second region is rotationally positioned with respect to the first region so that it partially overlaps the first region at points of intersection of the two regions. These points of intersection are the rectifying junctions. The respective shapes of the opening and of the second region are arranged so that the sum of the areas of the breakdown junctions is a constant value notwithstanding that the second region may be displaced or misaligned with respect to the first region, provided that relative displacement or misalignment of the two regions is within defined limits.

Diode structure

An amplifying circuit comprises a differential amplifier receiving input signals and having first and second output connections to which the input and output connections of a current amplifier respectively connect. A transistor receives signals at its gate from the second output connection of the differential amplifier and has a capacitor connected between its input and output electrodes. A feed-forward circuit, responsive to signals at the first output connection of the differential amplifier, develops a feed-forward signal which is applied to the output electrode of the transistor and poled so as to reinforce the signals thereat. The feed-forward signals tend to cancel signals conducted through the capacitor at high frequencies where the transistor exhibits reduced gain.

Operational amplifier with feed-forward compensation circuit

A semiconductor power device comprises a semiconductor pellet having first and second opposing major surfaces, including, in series, emitter, base and collector regions of alternate conductivity type. The collector region is substantially planar and adjacent to the second surface, the base region is adjacent to the collector region and extends to the first surface, and the emitter region extends relatively deeply into the pellet from the first surface and is substantially surrounded by the base region. The emitter region substantially surrounds a substantially centrally located extension of the base region, this extension being of relatively high resistance and also terminating at the first surface. An emitter electrode contacts the emitter region and the base region extension, a collector electrode contacts the collector region, and a base electrode contacts the base region.

Semiconductor power device having second breakdown protection

A semiconductor power device comprises a semiconductor pellet having first and second opposing major surfaces, including, in series, emitter, base and collector regions forming a PNP transistor. The collector region is substantially planar and adjacent to the second surface; the base region is adjacent to the collector region and extends to the first surface; and the emitter region extends into the pellet from the first surface such that it is substantially surrounded by the base region. The emitter region substantially surrounds a substantially centrally located extension of the base region which also terminates at the first surface. Emitter, base and collector electrodes are ohmically disposed on the respective semiconductor regions and a Schottky barrier contact is formed on the base region extension, the Schottky contact being connected to the emitter electrode.

Semiconductor power device incorporating a schottky barrier diode

An electronic timing circuit for an internal combustion engine includes a Schmitt trigger operated by timing pulses from a magnetic pick-up mounted on the engine. The upper trip point is set high when the pulses have a high amplitude due to a high engine speed, so that false triggering of the circuit by noise of lower amplitude is avoided. A lower trip point is automatically set when the pulses have a low amplitude, such as when the engine is cranked to start it.

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Somerville, NJ, United States of America

John A Olmstead