International Business Machines Corporation

Other

John A Murdock

Agnes Yee Ngai

Charles E Boice

Barbara A Hall

Edward Francis Westermann

Stephen Philip Pokrinchak

John Mark Kaczmarczyk

Michael Patrick Vachon

James David Greenfield

Robert L Woodard

Everett G Vail, Iii

A method and system for encoding digital video picture data. In accordance with this method, the video picture data is partitioned into a group of blocks, at least some of those blocks are selected, one block at a time, and each of the selected blocks of data is encoded to form an encoded coefficient having an associated number of bits. The encoded coefficients are outputted, and an accumulated sum of the number of bits in the outputted encoded coefficients is kept. The outputting of the encoded coefficients is terminated at a defined time in order to prevent the accumulated sum from exceeding a given number.

Precise bit control apparatus with look-ahead for MPEG encoding

The Invention is a modular, flexible automobile turntable for installation on an uneven surface such as a residential driveway. A flexible track conforms to the surface of the driveway. A turntable deck is mounted for rotation on the track, the deck comprising a central disk driven by a hydraulic gear motor and a plurality of flexible petals extending radially from the center disk.

Automobile turntable

An apparatus used for video encoding MPEG compliant digital visual images, having multiple MPEG encoders used in the motion estimation function. The search capabilities used in the motion estimation function of a single MPEG encoder are extended beyond its design limitations as a result of utilizing more than one MPEG encoder. The utilization of multiple encoders effectively creates the capability for a user to specify a wider search window than what is available in a single encoder configuration. The computational search efficency associated with searching the wider window is not adversely affected as a consequence of the multiple processors subdividing the extended window and analyzing each subdivision in parallel.

Multiple encoder architecture for extended search

System for reducing power consumption in MPEG-2 compliant video encoder circuitry employs logic for controlling first clock signals input to functional I, HSU and RSU blocks and functional sub-units performing specific tasks therein. Second clock signals are continuously input to a processing detection circuits requiring continuous clock inputs throughout video encode operations for a functional sub-unit. A trigger signal is asserted by the sub-unit itself or, an external processor, to indicate idle or active processing for that particular sub-unit. The combination of the second clock signals and receipt of the trigger signal enable the sub-unit to generate a sleep signal for that sub-unit which is input to a clock control circuit to either enable input of first clock signals to the functional sub-unit during active processing or, disable input of the first clock signal during idle, in-active processing periods, for as long as the trigger signal is asserted. There are a variety of video input conditions that may be detected which will enable generation of a trigger signal indicating idle processing for one or more functional sub-units, including, for example, detection of still input pictures, fade sequences and specification of high bitstream output rates.

Apparatus and method for power reduction control in a video encoder device

A digital video encoder is provided having an enhanced search range for motion estimation and compensation. The encoder is adapted to define from a reference frame a diamond-shaped search window about a current position of a current macroblock to be encoded. The encoder partitions the diamond-shaped search window into multiple search regions and reassembles the multiple search regions into a rectangular search area. This rectangular search area is then used to search the diamond-shaped search window for a best matching reference macroblock to the current macroblock.

Video encoding motion estimation employing partitioned and reassembled search window

An MPEG2 compliant digital video encoder system employs an I-frame video encoder module having a quantization unit and variable length encoding to encode coefficients of each macroblock of a picture. Bit regulation schemes are presented for constraining selected coefficients of a macroblock if the bit rate of two prior macroblocks in a row exceeded a bit rate limit, or if the bit rate of the current nonintra macroblock is greater than a predetermined megabits per second (Mbps) limit. Pattern constraining is implemented within the quantization unit. For nonintra pictures, the conventional variable length coding process is modified to generate a Fixed Coded Block Pattern (FCBP) header for each macroblock of the picture for outputting in the bitstream prior to coding of the coefficients. The FCBP signifies that each block of the macroblock contains at least one nonzero coefficient. The regulation scheme then ensures that each block of the macroblock includes at least one nonzero coefficient by setting one of the coefficients in an all zeros block to a nonzero value.

Macroblock bit regulation schemes for video encoder

A method for compensating for reduced picture quality when combining a multi-chip encoding chipset into a single integrated semiconductor IC. The method includes additional functions provided on the single IC to compensate for the negative effects on picture quality produced as a result of rounding 8 bit luminance pixel data to 5 bits, where the luminance data values are supplied as input to the search function. The additional functions are collectively referred to as motion biasing and are applied to influence the choice of a 'best match' motion type, which is well known in the art. The biasing is performed by the addition of a weight factor to a total difference result that is calculated by the search function. The biasing is applied only for the purpose of influencing the choice of a reference frame that is not necessarily the frame which produces an optimal motion vector, but rather will result in using fewer bits to encode macroblocks.

Motion estimation architecture for area and power reduction

Method and apparatus for calculating motion vectors. The method and apparatus calculate a motion trajectory value and initial base weights such that when x is the horizontal offset of the current macroblock from the left edge of the search window, and y is the vertical offset of the current macroblock from the top edge of the search window, and this pair of x and y values are used as the initial base weights, the motion estimation provides the best matched macroblock that has the shortest distance from the current macroblock. When the initial base weights are set to 0's, then the motion estimation will produce the first best matched macroblock encountered by the search circuitry. A scheme is also provided to set the initial base weights so that the best matched macroblock closest to the motion trajectory is selected for the motion estimation.

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Apalachin, NY, United States of America

John A Murdock