Clear Logic, Inc.

Other

Integrated Device Technology, Inc.

Desa Ip, LLC

Netshape Components, Inc.

John A MacPherson

Alan H Huggins

Richard J Schmidley

Wendy Eng

Jayaraman R Iyer

William L Devanney

John Stanley Starzynski

James M Adee

David E Schmulian

Dennis L Lantz, Jr

Christopher H Schiller

Toby Frink

Keith R Erb

W James Corbett

The present invention is an indoor/outdoor patio heater which includes a base portion housing a gas source, a gas burner, gas valve, a fan under the burner to create twisting flame patterns and a liquid pump, a pair of concentric see-through tubular portions disposed vertically above said base portion and a top heat deflector portion, with the burner flame enclosed by the inner tubular portion and liquid flowing through the channel formed between the inner and outer tubular portions to create the appearance of a twisting flame enclosed within a waterfall. The invention can be utilized with its aesthetic flame features and its aesthetic water features together, or one or the other.

Indoor/outdoor patio heater fire sculpture

A realistic gas fire log system providing log movement during use to enhance the realism of a fireplace system, comprising a ceramic fiber top, molded to look like charred embers or ash ported with one or more holes and recessed at the bottom to form a cavity, a steel pan sealed to the bottom of the ceramic fiber top, forming a chamber; a gas supply, gas control valve and a venturi fitted in an orifice through the pan, and including a log movement mechanism comprising an armature for pivotable attachment to one end of a fire log resting over a second fire log including two or more log sections connected by a spring and an activating mechanism, which armature causes the hinged log to collapse downwardly when activated and reposition into its original position when the fireplace is turned off. The log movement mechanism can be incorporated into existing gas fire log systems or made part of the original equipment of a gas fire log system.

Gas fire log system with collapsing logs

According to the present invention, after manufacture of a disconnect fuse circuit, windows are opened in the insulating film overlying the second interconnect layer at all possible disconnection points, the disconnection points preferably being an exposure window that is aligned over a disconnect fuse circuit that includes a via that electrically connects electrical conductors disposed on different respective layers. This insulating film may consist of one or more layers of one or more materials, but preferentially consists of a single layer of silicon oxide. The wafer is then stored for later configuration. When the wafer is to be configured, a non-precision mask is manufactured. The wafer is coated with photoresist and patterned using the mask to produce disconnection holes in the photoresist at the desired disconnection points. Since the area over the desired disconnection points are free of the insulating film overlying the second patterned interconnect layer, the etching process can be limited to etch techniques which are optimized to etch metal with selectivity to the insulating film. The areas at the disconnection sites that are covered by the insulating film are further protected during the etch process, since the insulating film acts as an etch barrier to inhibit the etching of active circuit elements in proximity to the desired disconnect points.

Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter

A vertical fuse structure and methods for customization of integrated circuits include a substantially vertically-oriented interconnect structure or &ldquo;fuse&rdquo; which provides for a more densely packed and thus smaller programmable integrated circuit. In a preferred embodiment, a vertical interconnect structure is fabricated by forming a first interconnect layer, forming an insulating layer over the first interconnect layer in which substantially vertically-oriented vias are patterned in contact with the first interconnect layer, filling the vias with a conductive plug, and forming a second interconnect layer over the insulating layer in contact with the conductive plug. The vertical interconnect structure is preferably disconnected by forming a narrow, substantially vertical disconnect cavity through the second interconnect layer and a portion of the conductive plug, thereby removing the connection between the second interconnect layer and the plug.

Vertical fuse structure for integrated circuits and a method of disconnecting the same

A bond pad structure is provided which has a primary bond pad region electrically connected to a secondary bond pad region. The secondary bond pad region is used to test a circuit for configuration, while the primary bond pad is covered with a protective oxide. After configuration and etching to complete desired disconnections, the oxide is removed from the primary bond pad region, leaving an undamaged surface for subsequent wire bonding. The primary bond pad region and the secondary bond pad region can be a unitary structure or two separate structures.

Sacrificial bond pads for laser configured integrated circuits

Methods of designing integrated circuit gate arrays include the step of generating a netlist for a gate array integrated circuit having at least first logic and signal resources therein, directly from bitstream data which characterizes a programmable logic device having a first operational functionality and the first logic and signal resources as well. The generating step is also followed by the step of using the netlist to configure the first logic and signal resources within the gate array integrated circuit to provide the first functionality. A preferred integrated circuit design system is also provided and includes a programmable logic device having pre-programmed logic and signal resources therein and a gate array device having base logic and signal resources therein which are equivalent to the unprogrammed logic and signal resources of the programmable logic device. A computer-based apparatus is also provided for decoding a bitstream that characterizes the programmable logic device having a first operational functionality when programmed, into a netlist that designates electrical connections in the gate array device when wired to have the first operational functionality, and to provide a method for generating scan-based test vectors to verify the first functionality. Accordingly, when switching from a functional programmable logic device (PLD) implementation to a gate array implementation, it is unnecessary to start the design process over from scratch by performing logic synthesis, place and route and other front end design operations associated with conventional gate array design techniques.

Designing integrated circuit gate arrays using programmable logic device bitstreams

A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.

Modified lead frame for improved parallelism of a die to package

Method of improving parallelism of a die to package using a modified lead frame

A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Inter-conductive layer fuse for integrated circuits

A process for packaging a die uses compressible microspheres to form a stress buffer layer between the die and an epoxy encapsulant to absorb stresses on the die caused by the different thermal expansion rates of the epoxy and die during temperature changes. By using a compressible layer of microspheres or other material, the need for a nitride passivation or other insulating layer to protect the die from thermally-induced stress is eliminated. In addition, the number and size of the microspheres and the amount of epoxy used to seal the package can be adjusted so that the epoxy is approximately co-planar with the top of the package to allow the package to be handled and used with standard equipment and processes.

Using microspheres as a stress buffer for integrated circuit prototypes

A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with a standard precision mask to define all possible connections, vias or cut-points, and 2) using a targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Method of customizing integrated circuits by selective secondary

Die structure using microspheres as a stress buffer for integrated

A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations on a second photoresist layer, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.

Method of customizing integrated circuits by depositing two resist

A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.

Growing community of inventors

Front Royal, VA, United States of America

John A MacPherson