Compaq Computer Corporation, Inc.

John A Landry

Paul R Culley

Dale J Mayer

Javier F Izquierdo

Gary W Thome

Randy M Bonella

Paul A Santeler

James J Ganthier

Thanh Thien Tran

Michael J Collins

John S Thayer

David R Wooten

Roger E Tipley

Jeff W Wolford

Christopher C Wanner

Robert F Watts

Walter G Fry

Guy E McSwain

Lee B Hinkle

Harry R Rogers, Jr

A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

Multiprocessor communication using reduced addressing lines

Multiprocessor system including interprocessor encoding and decoding

A computer system including a modular keyboard assembly allows input device modules to be inserted into the keyboard assembly. The modular keyboard assembly includes a plurality of recessed opening in which an input device module can be inserted. A connector on the input device module mates with a connector in the recessed opening, thereby providing electrical contact between the input device module and the keyboard assembly. Each input device module can be replaced by the user with a different input device module providing flexibility to the user as well as minimizing the amount of cabling that typically confronts the user. A controller in the keyboard assembly determines the types of input device modules coupled to the keyboard assembly.

Modular keyboard for use in a computer system

An audio circuit for a computer includes a bidirectional modem connection, a microphone input, first and second audio output channels, and an audio synthesizing circuit arranged to produce first and second synthesized audio channels. In a first mode of operation the first synthesized audio channel is applied to the first audio output channel and the second synthesized audio channel is applied to the second audio output channel. In a second mode of operation the first and second synthesized audio channels are combined into a monotonic signal and applied to the second audio output channel, and audio signals from the bidirectional modem connection are applied to the first audio output channel.

Audio circuit for use with synthesized audio signals and signals from a

A memory controller dynamically predicts whether a next memory cycle which is not yet available will result in a page miss or page hit condition. RAS lines are selectively precharged if the next memory cycle is predicted to be a page miss. The memory controller keeps track of various combinations of types of cycles when a type of memory cycle is followed by a type of non-memory pending cycle. For each such combination, the memory controller determines the percentage of combinations which result in a page hit on the next memory cycle. Using this history, the memory controller selectively precharges the RAS lines when a certain combination of types of cycles indicates a percentage of hits is below a predicted threshold. If a number of page hits exceeds the predicted threshold, precharging is not performed.

Memory controller that dynamically predicts page misses

A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine completes its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Fully pipelined and highly concurrent memory controller

A multiplexed communication protocol for broadcasting interrupt, DMA and other miscellaneous data across a bus from a central peripheral device to a plurality of distributed peripheral devices associated with each processor in a multiprocessor computer system. The multiplexed bus includes a data portion and a status portion, where the status portion indicates one of several different cycle types executed on the bus, and where each cycle type further indicates the data asserted on the data portion. The cycle types further include address and data read and write cycles to allow access of the registers in the distributed devices via the multiplexed bus. Thus, system interrupt, address, data, DMA, NMI and miscellaneous cycles are defined where a system interrupt cycle is continually executed on consecutive cycles until interrupted by a request to execute another cycle type. The cycle sequence is implemented to insert system interrupt cycles between the address and data cycles to prevent significant channel latency when system interrupts occur.

Multiplexed communication protocol between central and distributed

An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Arrangement of DMA, interrupt and timer functions to implement

A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Method and apparatus for testing and debugging a tightly coupled

A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

Automatic logical CPU assignment of physical CPUs

Filtering logic coupled between the microprocessor and the host bus to decode illegal special cycles executed by the processor to prevent these cycles from appearing on the host bus, which would otherwise be misinterpreted by logic coupled to the host bus. In the preferred embodiment, a modularized computer system based primarily on the 80386 or i486 microprocessors by Intel is upgraded to the new P5 or Pentium processor, also by Intel. The host and I/O buses are not modified and operate at the same speed and data width as in the previous systems. A processor board is upgraded with the P5 processor and includes the filtering logic according to the present invention. The P5 processor includes 8 byte enable bits as compared to the 4 byte enable bits used by the microprocessors 80386 and i486. Two new special cycles supported by the P5 processor are not supported by the previous host bus and would cause erroneous operation if allowed to be executed on the host bus. The filtering logic detects the two new cycles and prevents the cycles from being passed to the host bus.

Apparatus for asserting an end of cycle signal to a processor bus in a

A computer system includes a filter at an interrupt request input for a microprocessor system. The interrupt signal filter suppresses any positive pulse that is shorter than 9 cycles of the host clock. Only signals that are asserted for at least 17 HCLK cycles are guaranteed passage to the interrupt controller to assert the interrupt request. In addition, any negative pulse on the IRQ signal is latched and extended for at least 9 cycles of the host clock. The filter thus suppresses noise to prevent unnecessary interrupts, and provides for enhanced detection of negative levels and rising edges for negative-going interrupt request signals.

Positive pulse format noise-filter and negative pulse format extension

A method and apparatus which maintains strict ordering of processor cycles to guarantee that a processor write, such as an EOI instruction, is not executed to the interrupt controller prior to the interrupt request from a requesting device being cleared at the interrupt controller, thus maintaining system integrity. Interrupt controller logic is included on each respective CPU board. The processor can access the interrupt controller over a local bus without having to access the host bus or the expansion bus and thus an interrupt controller access could be completed before a previously generated I/O cycle has completed. Therefore, the apparatus which tracks expansion bus cycles and interrupt controller accesses and maintains strict ordering of these cycles to guarantee that an interrupt request is cleared at the interrupt controller prior to execution of write operation to the interrupt controller.

Apparatus for strictly ordered input/output operations for interrupt

A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

Memory accessing system with an interface and memory selection unit

The main system printed circuit board of a computer is mounted on a tray structure that also supports other CPU components of the computer and is removably insertable into the housing portion of the computer. A specially designed card edge connector portion of the system board is operatively insertable into a socketed connector on another circuit board interiorly mounted within the housing. Electrically conductive signal fingers and grounding fingers are respectively mounted on first and second sides of the card edge, with the signal fingers being connected to the signal plane of the system board, and the grounding fingers being connected to its ground plane. A sacrificial grounding pad is positioned on the second side of the edge connector portion, between the grounding pads and its leading edge, and is initially engaged by the internal connector contact strips, as the card edge is being inserted into the connector, to equalize any voltage potential between the two circuit boards before the contact strips engage the signal and grounding fingers The grounding pad thus eliminates the necessity of incorporating clamping diodes in the system board circuitry to avoid ESD damage to its components. The initially engageable grounding pad also serves as a sacrificial contact wear member that lengthens the connectivity life of the system board by diminishing the mechanical wear-away of the signal and grounding fingers.

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Tomball, TX, United States of America

John A Landry