National Semiconductor Corporation

John A Jackson

Nikhil Vishwanath Kelkar

William Jeffrey Schaefer

A chip-on-chip integrated circuit package is disclosed. The device includes a substrate having a plurality of conductive landings disposed on a first surface thereof, a first die that is positioned over a substrate, and a second die that is mounted on the first die. The first die has a plurality of I/O pads that face away from the substrate. The second die includes a first set of contacts that mate with the conductive landings on the substrate and a second set of contacts that mate with the I/O pads on the first die. In a preferred embodiment, the first set of contacts on the second die take the form of a first set of solder bumps, and the second set of contacts on the second die take the form of a second set of solder bumps. The device may also include a die attach material for attaching the first die to the substrate, wherein the die attach material and the first and second sets of solder bumps have a configuration that facilitates bonding and at least a portion of each of the solder bumps in the first and second sets of solder bumps and the die attach material have a substantially common reflow temperature. A method for making a chip-on-chip integrated circuit package is also disclosed.

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Sunnyvale, CA, United States of America

John A Jackson