Tektronix, Inc.

John A Hengeveld

Jonathan C Lueker

Mehrab Sedeh

Burt L Price

Jim Schlegel

Brad Needham

Bradford H Needham

Roy I Siegel

James Schlegel

A visually graded display of digitally compressed waveforms for a digital storage oscilloscope. A histogram is formed by sampling or otherwise resolving a data set of values corresponding to an independent variable to produce a quantized set of values over a selected compression interval of the independent variable. The compression interval represents equal quanta of the independent variable and has associated therewith a set of histogram bins, each containing a number, wherein the number contained within each bin represents a weighted number of hits associated with vectors connecting selected pairs of such dependent variable values, wherein each vector is associated uniquely with one pair. The numbers are weighted for each vector according to drawing techniques, the drawing techniques alone or in combination allowing choices for signal display ranging between retaining maximal signal information, for emulating the display of an analog oscilloscope, or retaining less signal information. The numbers within the histogram bins are representative of an accumulation of vectors within a compression interval and are mapped to a display having a data axis and an independent variable axis. The mapping associates the contents of the histogram bins to a portion of the display and provides for the gradation of a visual characteristic, such as intensity or color, to represent, along the data axis, the data set of values.

Graded display of digitally compressed waveforms

A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or 'slivers' and very small analog increments or 'verniers'. In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included. This architecture provides controllable tolerances, permits accurate positioning of a trigger out signal relative to any pulse produced, allows the user to specify the trailing edge timing directly, and permits both pulse width and phase to be specified as a percentage of the overall period and automatically kept proportional when the frequency is varied. It also allows synchronized operation of different channels at rates related by powers-of-two, and permits the disabling of a channel at an operator determined voltage level. A means for determining, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, is also provided.

Digital pulse generator

A digital data generation system including a programmable dominance RS flip-flop has a random access memory that stores a user selected sequence of test data. A pattern formatting logic circuit receives the test data and produces, for each data period, a coarsely timed candidate pulse for identifying the leading edge of an output data pulse and a coarsely timed candidate pulse for identifying the trailing edge of the output data pulse. A precision delay circuit finely tunes the timing of the candidate pulses. The finely tuned pulses are applied to an RS flip-flop circuit which can be programmed for set or reset dominance, thereby preventing an indeterminate state when a logic '1' is applied to both the set and the reset input. In the system, the flip-flop is programmed so that the most recent of the lead pulse or the trail pulse prevails.

Digital data generation system including programmable dominance latch

A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or 'slivers' and very small analog increments or 'verniers'. In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included. This architecture provides controllable tolerances, permits accurate positioning of a trigger out signal relative to any pulse produced, allows the user to specify the trailing edge timing directly, and permits both pulse width and phase to be specified as a percentage of the overall period and automatically kept proportional when the frequency is varied. It allows synchronized operation of different channels at rates related by powers-of-two, and permits disabling of a channel at an operator determined voltage level. A means for determining, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, is also provided.

Digital pulse generator using digital slivers and analog vernier

A digital architecture for a pulse generator provides a method of synchronizing signals of the pulse generator. The pulse generator has a timebase card, a microprocessor and a plurality of pulse cards. The microprocessor controls the parameters of the timebase card and pulse cards, and the timebase card provides a common master clock signal to all of the pulse cards determined by a triggerable voltage controlled oscillator that has two sources of frequency control voltage, an internal DAC for absolute frequency and a frequency comparison circuit for synchronization with an external timebase. The pulse cards produce pulses, either singly or in bursts, with the leading and trailing edges being separately positionable using quantum, sliver and vernier controls. A pattern RAM on each pulse card provides a pulse pattern that provides an approximation of the desired pulses to one quantum, and repeated iterations through the pattern RAM provide bursts of pulses. Pattern RAMs on different pulse cards, where one pattern is related to the other by a power of two, may be synchronized since both channels use the same master clock from the timebase card. Likewise a burst of pulses may be synchronized with the external timebase since the master clock is synchronized with the external timebase, with a frame sync input signal being used to determine the relative phase between the burst of pulses and the external timebase.

Growing community of inventors

Aloha, OR, United States of America

John A Hengeveld