Analog Devices,inc.

Analog Devices Global Unlimited Company

John A Hayden

Gordon Cheung

Gregory T Koker

Richard F Grafton

Hans Brueggemann

Matthew Puzey

Ahmed Ali Mohamed

James Frank Galeotos

Hans Brueggmann

Switching interference is a primary artifact which affects the accuracy of arc detectors. To address switching interference, conventional arc detectors employ computationally intensive techniques which are often designed specifically for a target application. Thus, conventional arc detectors require a significant amount of hardware to accurately detect arc faults, which can increase costs of the power systems and prohibit wide deployment of arc detectors. With improved signal processing, a unique method for arc detection can accurately detect arc faults efficiently while tolerate switching interference from an inverter of the power system. Specifically, the method provides accurate but efficient arc detection by using a small Fast Fourier Transform with coherent sampling that is accomplished with a common clock generator in combination with signal conditioning. The overall system implementing the method is also programmable to suit a variety of target applications.

Computationally efficient arc detector with coherent sampling

In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from faults in the interconnect itself or in any of the connected peripherals. To provide sufficient fault tolerance, a safety node is inserted between an upstream master section and a downstream slave section of an on-chip bus hierarchy or network. The safety node provides a programmable timeout monitor for detecting a timeout condition for a transaction. If timeout has occurred, the safety node transmits a dummy response back to the master, assumes the role of a master, and waits for the slave device to respond. Furthermore, the safety node rejects any subsequent requests by any of the masters on the upstream section by transmitting a dummy response to those subsequent requests, thus enabling these masters to avoid deadlock or stall.

Safety node in interconnect data buses

A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses; and a multiplexer configured to supply first and second current memory addresses to selected ones of the first and second memory pipelines in response to a control signal.

DMA controller for digital signal processors

A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. Channel control logic controls transfer of data through the DMA channels in response to parameters contained in at least one DMA descriptor having a programmable format.

DMA controller utilizing flexible DMA descriptors

A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

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Sharon, MA, United States of America

John A Hayden