International Business Machines Corporation

John A Gerardi

Bruce L McGilvray

Shiu K Chan

A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the associated cache line, which operations are allowed when the lock bit is off. The lock bit may be in an off state while an associated valid bit is set on, but once the lock bit is set on the valid bit cannot be set off until the lock bit is first set off. Lock array controls operate with a replacement selection circuit (which may be conventional) to eliminate each locked line from being a replacement candidate in its congruence class in a set-associative store-in-cache in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the status of the associated cache directory. A special type of IE operand request, called a store-interrogate (SI) request, is used to lock the accessed line, whether or not the SI request hits or misses in the cache. Any locked line can continue to receive any fetch, SI, or store cache request from its own IE. Any line remains unlocked as long as it is not accessed by a SI request; that is a line remains unlocked as long as it only receives fetch requests, and fetch requests are generally much more numerous than SI requests. Line locking enables the castout or invalidation of unlocked cache lines during a checkpoint interval.

Cache locking controls in a multiprocessor

The disclosure detects and handles synonyms for a store-in-cache (SIC). A processor cache directory (PD) is searched in a principle class addressed by a subset of bits taken from a processor request's logical address. The class address has both translatable and non-translatable bits. If any of the set-associative line entries in the principle class contains the request's translated address, the data is accessed in a corresponding line location in the cache. If the principle class does not have any entry with the request's translated address, a cache miss signal occurs which causes a line fetch command to be generated for main storage to fetch the required line. The line fetch command also causes synonym search circuits to generate the address of every potential synonym class by permutating the translatable bits in the principle class address provided in the line fetch command. Then each potential synonym class is accessed in a copy directory (CD) (which is a copy of essential information in all entries in PD) and compared to the translated request address in order to detect for any existing synonym. Each line entry in the PD and CD also has an exclusive (EX) shareability control bit which controls the handling of a request after detection of a synonym in the CD. If the EX bit is off representing a read only (RO) state, the line cannot be locked during any checkpoint interval. Then the data is not accessed in the detected synonym location, but instead the RO line is copied into an entry in the principle class to improve system performance due to subsequent requests expected to the same line. The synonym line is not invalidated unless the processor is requesting the data exclusively (EX). If the EX bit is on representing an exclusive state in a found synonym entry, the line may be locked in the cache during a checkpoint interval, and therefore the data is accessed in the detected synonym location in the SIC because it cannot then be moved.

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Poughkeepsie, NY, United States of America

John A Gerardi