Gte Automatic Electric (canada) Limited

Gte Automatic Electric Laboratories Incorporated

Gte Automatic Electric Labs Inc.

John A Gauthier

David Michael Shaver

Robert M Thomas

John R Ramsay

Thomas J Moorehead

A telephone ringing signal generator which sequentially produces a plurality of ringing signals each of a different frequency. Each of a plurality of tone ringers connected to the generator will ring only in response to it's particular frequency. A programmable oscillator generates the required frequencies under control of a time slot generator which defines the time slot during which each frequency is to be generated.

Ringing signal generator

A telephone ringing signal generator which produces a signal that can ring a plurality of connected ringers tuned to different frequencies. The ringing signal comprises sequentially varying frequencies and each ringer will ring in response to its particular frequency. A counter is used to define the duration of the ringing signal and enable each frequency sequentially. A variable sweep frequency oscillator is connected to the counter and generates a signal having a different frequency for each counter increment. A programmable filter shapes the signal into a sine wave which is amplified to ringing voltage levels by a ringing signal amplifier.

A control point driver circuit for use in a telephone exchange for energizing and deenergizing a control element such as a control relay in response to set and reset input pulses. The control point driver circuit comprises a transformer having a centertapped primary forming set, reset, and common inputs for receiving the set and reset input pulses and a secondary coupled to a constant control voltage. The control point driver circuit also includes a comparator having a first input coupled to the transformer secondary, an output coupled to the control relay to be energized and de-energized and a second input coupled to the comparator output for receiving first and second reference voltages which are related in magnitude to the constant control voltage to maintain the comparator in the set state or reset state indefinitely until a reset or set input pulse is received. A received input pulse causes an induced voltage within the transformer secondary which augments the control voltage to change the relation in magnitude between the reference voltages and the control voltage to cause the comparator to change states in response to the received set and reset input pulses. When the comparator is in the set state, the control relay is energized and when the comparator is in the reset state, the control relay is de-energized.

Control point driver circuit

The disclosure relates to a control means for converting serially transmitted di-phase data bits into parallel data bits having corresponding discrete logic levels. The control means of the present invention is adapted for use in a di-phase pulse receiving system of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di-phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion. The control means comprises a first set means coupled to the positive peak detector and responsive to the first pulses for being set upon the detection of a positive di-phase signal portion, a second set means coupled to the negative peak detector and responsive to the second pulses for being set upon the detection of a negative di-phase signal portion, and a shift register means having a first input coupled to the first set means, a second input coupled to the second set means, a clock input coupled to the positive detector for being clocked by the trailing edge of the first pulses, and a plurality of parallel outputs. The shift register means is responsive to the coincidence of the first and second set means being set upon being clocked to thereby shift a first logic level to the parallel output and is responsive to only the first set means being set upon being clocked to thereby shift a second logic level to the parallel output.

Di-phase pulse receiving system

A register and sender module with an internal common control provided with common addressing, storage, and timing for up to four registers, up to two senders, and up to two tone control circuits in a module. Modular construction allows addition and replacement of the various circuits in the module on an as required basis with a minimum of rewiring. An internal bus couples all module circuits to the internal common control. Each register and sender in the module is accessible from every inlet to the module. Provision is made for single digit storage to the registers and senders and single digit read out from the sender.

Modular register and sender arrangement

A dial pulse receiver having a clock pulse input to a counter and a first and second flip-flop. The outputs of the two flip-flops are coupled to an exclusive OR gate to reset the counter. The counter output and the two outputs of the second flip-flop are coupled to an output gate and latch configuration. The counter is set to enable the latches so only a legitimate dial pulse is recorded.

Dial pulse receiver

A TCMF and MF decoder with common decoder section and separate TCMF and MF control sections. The decoder is time shared between two or more registers served on a first-come, first-served basis with priority assigned to one in case of identical seizure time. Strapping options are provided to allow the two registers to be both TCMF registers, or both MF registers, or one of each.

Time shared TCMF and MF decoder

A side of line detector with a single operational amplifier with adjustable output. The amplifier input is protected from positive and negative voltage spikes by diodes. Two transistors are coupled to the amplifier to set a comparator voltage reference which allows the rejection of leakage and noise. Test points are provided in the circuit to facilitate testing particular subcircuits and to allow the initial adjustment of the detector.

Electronic side of line detector

A shift register is provided with two inputs and two outputs. One input is from a free running clock and a second input is provided for relay operate and release signals. The two outputs are coupled to a NAND gate to provide a longer relay operate than release time. The two outputs are coupled to a NOR gate for a longer relay release time than operate time. Either gate output is coupled to a relay driver to operate the relay.

Growing community of inventors

Brockville, Canada

John A Gauthier