Agere Systems Inc.

American Telephone & Telegraph Co., At&t Bell Laboratories

Agere Systems Guardian Corp.

John A Carelli, Jr

Malcolm Harold Smith

Robert Leonard Pritchett

Fan Zhou

Richard A Pedersen

A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A model of the cell is generated which stores an identifier of the characterization driver in association with an identifier of the input. The cell model is then utilized to determine if an actual driver of the input of the cell in the integrated circuit design has a drive strength which is less than that of the characterization driver, and if the actual driver has a drive strength which is less than that of the characterization driver an indicator of this condition is generated. The indicator may, for example, prompt selection of a different driver to replace the actual driver in the integrated circuit design.

Cell modeling for integrated circuit design with characterization of upstream driver strength

Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage slew, capacitive load, supply voltage or temperature. Error values are generated indicative of error between the measured data points and the full-space polynomial model. The error values are used to partition the modeling space into domains. For at least a given one of the domains, a first polynomial model is generated based on a subset of the measured data points and at least one additional data point determined by interpolation from the measured data points in the subset. Error values are generated indicative of error between the measured data points of the subset and the first polynomial model. A shifted model is generated by applying correction factors determined from the error values to respective data points taken from the first polynomial model. A second polynomial model of the given domain is generated by fitting to a plurality of data points from the shifted model.

Multi-variable polynomial modeling techniques for use in integrated circuit design

The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.

Apparatus and method for determining process width variations in integrated circuits

An integrated circuit includes first and second field effect transistors having differing channel lengths, and a means for comparing the channel currents flowing therethrough. An excessive difference of currents indicates 'short channel' effects, which can degrade performance. A signal flag indicating this condition may be provided to a test pad on the chip, or used to disable operation of the integrated circuit, or otherwise used to provide an indication.

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Allentown, PA, United States of America

John A Carelli, Jr